- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67335 > 5962-9203501MCA (NATIONAL SEMICONDUCTOR CORP) 2-CHANNEL, SGL ENDED MULTIPLEXER, CDIP14 PDF資料下載
參數(shù)資料
| 型號(hào)： | 5962-9203501MCA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 多路復(fù)用及模擬開關(guān) |
| 英文描述： | 2-CHANNEL, SGL ENDED MULTIPLEXER, CDIP14 |
| 封裝： | CERDIP-14 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大小： | 277K |
| 代理商： | 5962-9203501MCA |
Power Supplies and Grounding
Proper power supply bypassing and grounding is essential to
the CLC532’s operation.
A 0.1
F to 0.01mF ceramic chip
capacitor should be located as close as possible to the individual
power supply pins. Larger +6.8
F tantalum capacitors should
be used within a few inches of the CLC532.
The ground
connections for these larger by-pass capacitors should be very
symmetrically located relative the CLC532 output load ground
connection. Harmonic distortion can be heavily influenced by
non-symmetric decoupling capacitor grounding. The smaller
chip capacitors located directly at the power supply pins are not
particularly susceptible to this effect.
Separation of analog and digital ground planes is not
recommended. In most cases, a single low-impedance ground
plane will provide the best performance. In those special cases
requiring separate ground planes, the following table indicates
the signal and supply ground connections.
Pin
Functions
Ground Return
1,3
Shield /Supply Returns Supplies and Inputs
5D
REF Ground
D
REF Currents Only
Input Shielding
The CLC532 has been designed for use in high-speed wide-
dynamic range systems. Guard-ring traces and the use of the
ground pins separating the analog inputs are recommended to
maintain high isolation (Figure 6). Likely sources of noise and
interference that may couple onto the inputs, are the logic signals
and power supplies to the CLC532. Other types of clock and
signal traces should not be overlooked, however.
Channel A
Connector
Channel B
Connector
Chip Resistors
Pin 1
Figure 6: Alternate Layout Using Guard Ring
The general rule in maintaining isolation has two facets, minimize
the primary return ground current path impedances back to the
respective signal sources, while maximizing the impedance
associated with common or secondary ground current return
paths. Success or failure to optimize input signal isolation can
be measured directly as the isolation between the input channels
with the CLC532 removed from circuit. The channel-to-channel
isolation of the CLC532 can never be better than the isolation
level present at its inputs.
Special attention must be paid to input termination resistors.
Minimizing the return current path that is common to both of the input
termination resistors is essential. In the event that a ground return
current from one input termination resistor is able to find a secondary
path back to its signal source (which also happens to be common
with either the primary or secondary return path for the second input
termination resistor), a small voltage can appear across the second
input termination resistor. The small voltage seen across the
second input termination resistor will be highly correlated with the
signal generating the initial return currents.
This situation will
severely degrade channel-to-channel isolation at the input of the
CLC532, even if the CLC532 were removed from circuit. Poor
isolation at the input will be transmitted directly to the output.
Use of "small" value input termination resistors will also improve
channel-to-channel isolation. However, extremely low values
(<25
) tend to stress the driving source's ability to provide a high-
quality input signal to the CLC532.
Higher values tend to
aggravate any layout dependent crosstalk. 75
to 50 is a
reasonable target, but the lower the better.
Combining Two Signals in ADC Applications
The CLC532 is applicable in a wide range of circuits and
applications. A classic example of this flexibility is combining two
or more signals for digitization by an analog-to-digital converter
(ADC). A clear understanding of both the multiplexer and the
ADC's operation is needed to optimize this configuration.
To obtain the best performance from the combination, the output
of the CLC532 must be an accurate representation of the
selected input during the ADC conversion cycle. The time at
which the ADC samples the input varies with the type of ADC that
is being used.
Subranging ADCs usually have a Track-and-Hold (T/H) at their
input. For a successful combination of the multiplexer and the
ADC, the multiplexer timing and the T/H timing must be compatible.
When the ADC is given a convert command, the T/H transitions
from Track mode to Hold mode. The delay between the convert
command and this transition is usually specified as Aperture
Delay or as Sampling Time Offset.
To maximize the time that the multiplexer output has to settle, and
that the T/H has to acquire the signal, the multiplexer should
begin its transition from one input to the other immediately after
the T/H transition into HOLD mode. Unfortunately it is during the
initial portion of the HOLD period that a subranging ADC performs
analog processing of the sampled signal.
High slew rate
transitions on the input during this time may have a detrimental
effect on the conversion accuracy.
To minimize the effects of high input slew rates, two strategies
that can employed. Strategy one applies when the sample rate
of the system is below the rated speed of the ADC. Here the
CLC532 SELECT timing is delayed until after the multiplexer
transition takes place, and after the A/D has completed one
conversion cycle and is waiting for the next convert command.
As an example, if a CLC935 (15MSPS) ADC is being used at
10MSPS, the conversion takes place in the first 67ns after the
CONVERT command. The next 33ns are spent waiting for the
next CONVERT command, and would be an ideal place to switch
the multiplexer from one channel to the next.
Sample Rate (MSPS)
C
co
mp
(p
F)
10
11
12
13
14
15
16
17
18
19
20
50
45
40
35
30
25
20
15
10
5
Figure 7: Recommended C
COMP vs. ADC Sample Rate
The second optimization strategy involves lowering the slew rate
at the input of the ADC so that fewer high frequency components
are available to feed through to the hold capacitor during HOLD
7
http://www.national.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962-920401M2A | 8-CHANNEL, SGL ENDED MULTIPLEXER, CQCC20 |
| 5962-920402M2A | 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, CQCC20 |
| 5962-920401MEA | 8-CHANNEL, SGL ENDED MULTIPLEXER, CDIP16 |
| 5962-920402MEA | 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, CDIP16 |
| 5962-920402M2A | 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, CQCC20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-9204001HXA | 制造商:International Rectifier 功能描述:DC/DC CONVERTER, CLASS H - Rail/Tube |
| 5962-9204001HZA | 制造商:International Rectifier 功能描述:DC/DC CONVERTER, FLANGED, CLASS H - Rail/Tube |
| 5962-9204002HXA | 制造商:International Rectifier 功能描述:DC/DC CONVERTER, CLASS H, SLAVE - Rail/Tube |
| 5962-9204002HZA | 制造商:International Rectifier 功能描述:DC/DC CONVERTER, FLANGED, CLASS H, SLAVE - Rail/Tube |
| 5962-9204003HXA | 制造商:International Rectifier 功能描述:DC/DC CONVERTER, CLASS H, MASTER - Rail/Tube |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。