參數(shù)資料
型號(hào): 5962-8997401PA
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 運(yùn)算放大器
英文描述: OP-AMP, CDIP8
封裝: CERDIP-8
文件頁數(shù): 8/14頁
文件大?。?/td> 382K
代理商: 5962-8997401PA
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC)
±7V
I
OUT
Output is short circuit protected to
ground, but maximum reliability will
be maintained if I
OUT does not
exceed...
60mA
Common Mode Input Voltage
±V
CC
Junction Temperature
+150C
Operating Temperature Range
40C to +85C
Storage Temperature Range
65C to +150C
Lead Solder Duration (+300C)
10 sec
ESD Rating (Human Body Model)
<1000V
Recommended Gain Range
+7 to +50
1 to 50
Operating Ratings
Thermal Resistance
Package
(
θ
JC)(θJA)
MDIP
70C/W
125C/W
SOIC
65C/W
145C/W
Electrical Characteristics
(A
V = +32, VCC = ±5V,RL = 100,Rf = 1.5,VH = +3V; unless specified)
Symbol
Parameters
Condition
Typ
Max & Min Ratings(Note 2)
Units
Ambient Temperature
CLC501AJ
+25C
40C
+25C
+85C
Frequency Domain Response
SSBW
–3dB Bandwidth
V
OUT < 5VPP
75
>60
>45
MHz
SS20
–3dB Bandwidth
@A
V = +20, VOUT <
2V
PP
110
>85
>55
MHz
Gain Flatness
V
OUT < 5VPP
GFPL
Peaking
<15MHz
0
<0.1
dB
GFPH
Peaking
>15MHz
0
<0.2
dB
GFR
Rolloff
< 30MHz
0.2
<1.0
<1.3
dB
LPD
Linear Phase Deviation
DC to 30MHz
0.2
<1.0
deg
Time Domain Response
TRS
Rise and Fall Time
2V Step
4.7
<5.8
<7.8
ns
TRL
5V Step
5.5
<6.5
<8.0
ns
TSP
Settling Time to ±0.05%
2V Step
12
<18
<24
ns
OS
Overshoot
2V Step
0
<5
<5%
SR
Slew Rate
1200
>800
>700
V/s
Distortion And Noise Response
HD2
2nd Harmonic Distortion
2V
PP, 20MHz
45
<30
<33
<30
dBc
HD3
3rd Harmonic Distortion
2V
PP, 20MHz
60
<45
<50
dBc
Equivalent Input Noise
SNF
Noise Floor
>1MHz
158
<156
<155
dBm
(1Hz)
INV
Integrated Noise
1MHZ to 100MHz
28
<35
<40
V
Clamp Performance
OVC
Overshoot in Clamp
32x Overdrive
5
<15
%
TSO
Overload Recovery from Clamp
32x Overdrive
1
<3
<3ns
CDR
V
ioDrift after Recovery
150
<200
V
VOC
Clamp Accuracy(Note 3)
>2x Overdrive
0.1
<0.2
V
ICL
Input Bias Current on V
H,VL
20
<100
<50
A
CBW
–3dB Bandwidth
V
L,VH =2VPP
50
MHz
CMC
Useful Clamping Range
V
H or VL
<±3.0
<±3.3
V
Static, DC Performance
VIO
Input Offset Voltage(Note 3)
1.5
<4.6
<3.0
<5.0
mV
DVIO
Average Temperature
Coefficient
10
<20
<20
V/C
IBN
Input Bias Current(Note 3)
Non-Inverting
10
<37
<25
<35
A
CLC501
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