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參數(shù)資料
| 型號： | 5962-8997401PA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運算放大器 |
| 英文描述： | OP-AMP, CDIP8 |
| 封裝： | CERDIP-8 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 382K |
| 代理商： | 5962-8997401PA |
Application Division (Continued)
Clamp Operation
The maximum positive or negative excursion of the output
voltage is determine by voltage applied to the clamping pins,
V
H and VL.VH determines the positive clamping level; VL
determines the negative level. For example, if V
H is set at
+2V and V
L is set at 0.5V the output voltage is restricted
within this 0.5V to +2V range. When the output voltage tries
to exceed this level, the amplifier goes into “clamp mode”
and the output voltage limits at the clamp voltage.
Clamp Accuracy and Amplifier Linearity
Ideally, the clamped output voltage and the clamp voltage
should be identical. In practice, however, there are two
sources of clamp inaccuracy: the inherent clamp accuracy
(which is shown in the specification page) and resistor di-
vider action of open-loop output resistance of 10
and the
load resistor. Or, in equation form,
(1)
When setting the clamping voltage, the designer should also
recognize that within about 200mV of the clamp voltage,
amplifier linearity begins to deteriorate. (See plot on the
previous page.)
Biasing V
H and V L
Each of the clamping pins is buffered internally so simple
resistive voltage divider circuits work well in providing the
clamp voltages (see
Figure 3). The 100
isolating resistor
ensures stability when the clamp pin is connected to V
CC or
when the clamp pins is driven by an external signal source;
in other situations, such as the one described in
Figure 3, the
isolating resistor is not necessary.
V
H should be biased more positively than VL.VH may be
biased below 0V; however, with this biasing, the output
voltage will actually clamp at 0V unless a simple pull down
circuit is added to the op amp output. (When clamped
against V
H, the output cannot sink current.) An analogous
situation and design solution exists for V
L when it is biased
above 0V, but in this case, a pull up circuit is used to source
current when the amplifier is clamped against V
L
The clamps, which have a bandwidth of about 50MHz, may
be driven by high frequency signal source. This allows the
clamping level to be modulated, which is useful in many
applications such as pulse amplitude modulation. The
source resistance of the signal source should be less than
500
to ensure stability.
Clamp-Mode Dynamics
As can be seen in the clamped pulse response plot on the
previous page, clamping is virtually instantaneous. Note,
however, that there can be a small amount of overshoot, as
indicated on the specification page. The output voltage stays
at the clamp voltage level as long as the product of the input
voltage and the gain setting exceeds the clamp voltage.
When the input voltage decreases, it will eventually reach a
point where it is no longer trying to drive the output voltage
above the clamp voltage. when this occurs, there is typically
a 1ns “overload recovery from clamp,” which is the time it
takes for the op amp to resume linear operation. The normal
op amp parameters, such as the rise time, apply when the op
amp is in linear operation.
When the op amp is in clamp mode for more than about
100ns, a small thermal tail can be detected in the settling
performance. This tail, which has a maximum value of
200V referred to the input, is proportional to the amount of
time spent in clamp in clamp mode. In most applications, this
will have only a minor effect. For example, in a system with
a 100ns overdrive occurring with a duty cycle of 10%, the
input-referred tail is 20V which is only 0.001% of a 2V
signal.
DC Accuracy and Noise
Since the two inputs for the CLC501 are quite dissimilar, the
noise and offset error performance differs somewhat from
that of a standard differential input amplifier. Specifically, the
inverting input current noise is much larger than the
non-inverting current noise. Also the two input bias currents
are physically unrelated rendering bias current cancellation
through matching of the inverting and non-inverting pin re-
sistors ineffective.
In equation 3, the output offset is the algebraic sum of the
equivalent input voltage and current sources that influence
DC operation. Output noise is determined similarly except
that a root-sum-of-squares replaced the algebraic sum. R
s is
the non-inverting pin resistance.
PSRR and CMRR
The PSRR and CMRR performance plots on the previous
page show performance for a circuit set at a gain of +32 and
a source resistance of 0
. In current feedback op amps,
common mode and power supply variations manifest them-
selves in changes in the op amp’s bias currents (IBI for the
inverting input and IBN for the non-inverting input) and in the
offset voltage (VIO). At DC, these values are:
(2)
The total effect, as reference to the input, is given by the
following:
(3)
Where R
s
is the equivalent resistance seen by the
non-inverting input and R
eq is the equivalent resistance of Rg
in parallel with R
f.
Printed circuit Layout
As with any high frequency device, a good PCB layout will
enhance performance. Ground plane construction and good
power supply bypassing close to the package are critical to
achieving full performance. In the non-inverting configura-
tion, the amplifier is sensitive to stray capacitance to ground
at the inverting input. Hence, the inverting node connections
should be small with minimal coupling to the ground plane.
Shunt capacitance across the feedback resistor should not
be used to compensate for this effect.
Evaluation PC boards (part number CLC730013 for
through-hole and CLC730027 for SOIC) for the CLC501 are
available.
CLC501
www.national.com
8
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