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參數(shù)資料
| 型號： | 5962-8959834M7A |
| 廠商： | MICROSS COMPONENTS |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 45 ns, CDSO32 |
| 封裝： | CERAMIC, SOJ-32 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 212K |
| 代理商： | 5962-8959834M7A |
SRAM
MT5C1008
MT5C1008
Rev. 6.8 01/10
Micross Components reserves the right to change products or specications without notice.
1
FEATURES
High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS process
Single +5V (+10%) Power Supply
Easy memory expansion with CE1\, CE2, and OE\
options.
All inputs and outputs are TTL compatible
Micross Components uses die type Cy7C109B from
Cypress -6-T SRAM cell design
OPTIONS
MARKING
Timing
12ns access
-12 (contact factory)
15ns access
-15
20ns access
-20
25ns access
-25
35ns access
-35
45ns access
-45
55ns access
-55*
70ns access
-70*
Package(s)
Ceramic DIP (400 mil)
C
No. 111
Ceramic DIP (600 mil)
CW
No. 112
Ceramic LCC
EC
No. 207
Ceramic LCC
ECA
No. 208
Ceramic Flatpack
F
No. 303
Ceramic SOJ
DCJ
No. 501
Ceramic SOJ
SOJ
No. 507
2V data retention/low power
L
*Electrical characteristics identical to those provided for the 45ns
access devices.
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-89598
MIL-STD-883
GENERAL DESCRIPTION
The MT5C1008 SRAM employs high-speed, low
power CMOS designs using a four-transistor memory cell, and
are fabricated using double-layer metal, double-layer polysili-
con technology.
For design exibility in high-speed memory appli-
cations, this device offers dual chip enables (CE1\, CE2) and
output enable (OE\). These control pins can place the outputs
in High-Z for additional exibility in system design. All de-
vices operate from a single +5V power supply and all inputs
and outputs are fully TTL compatible.
Writing to these devices is accomplished when write
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.
Reading is accomplished when WE\ and CE2 remain HIGH
and CE1\ and OE\ go LOW. The devices offer a reduced
power standby mode when disabled, allowing system designs
to achieve low standby power requirements.
The “L” version offers a 2V data retention mode,
reducing current consumption to 1mA maximum.
128K x 8 SRAM
WITH DUAL CHIP ENABLE
For more products and information
please visit our web site at
www.micross.com
NC
1
32
VCC
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE\
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE\
A2
10
23
A10
A1
11
22
CE\
A0
12
21
DQ8
DQ1
13
20
DQ7
DQ2
14
19
DQ6
DQ3
15
18
DQ5
VSS
16
17
DQ4
NC
1
32
VCC
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE\
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE\
A2
10
23
A10
A1
11
22
CE\
A0
12
21
DQ8
DQ1
13
20
DQ7
DQ2
14
19
DQ6
DQ3
15
18
DQ5
VSS
16
17
DQ4
NC
1
32 VCC
A16
2
31 A15
A14
3
30 CE2
A12
4
29 WE\
A7
5
28 A13
A6
6
27 A8
A5
7
26 A9
A4
8
25 A11
A3
9
24 OE\
A2 10
23 A10
A1 11
22 CE\
A0 12
21 DQ8
DQ1 13
20 DQ7
DQ2 14
19 DQ6
DQ3 15
18 DQ5
VSS 16
17 DQ4
32-Pin DIP (C, CW)
32-Pin CSOJ (SOJ)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
32-Pin Flat Pack (F)
32-Pin LCC (ECA)
4 3 2 1 32 31 30
A12
A14
A10
NC
V
CC
A15
CE2
14 15 16 17 18 19 20
DQ2
DQ3
V
SS
DQ4
DQ5
DQ6
DQ7
5
6
7
8
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
29
28
27
26
25
24
23
22
21
WE
A13
A8
A9
A11
OE
A10
CE1
DQ8
\
6
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-8959834MMA | 制造商:Microsemi Corporation 功能描述:128K X 8 SRAM MONOLITHIC, DUAL CHIP SELECT, 5V, 55NS, 32 CLC - Bulk 制造商:Micross Components 功能描述:SRAM, 1MB - Trays |
| 5962-8959834MTA | 制造商:Microsemi Corporation 功能描述:128K X 8 SRAM MONOLITHIC, DUAL CHIP SELECT, 5V, 55NS, 32 FLA - Bulk 制造商:Micross Components 功能描述:SRAM, 1MB - Trays |
| 5962-8959834MUA | 制造商:Micross Components 功能描述:SRAM, 1MB - Trays |
| 5962-8959834MXA | 制造商:Micross Components 功能描述:SRAM, 1MB - Rail/Tube |
| 5962-8959834MYA | 制造商:Microsemi Corporation 功能描述:128K X 8 SRAM MONOLITHIC, DUAL CHIP SELECT, 5V, 55NS, 32 CSO - Bulk 制造商:Micross Components 功能描述:SRAM, 1MB - Trays |
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