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參數(shù)資料
| 型號： | 5962-8768105VEA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2.2 A SWITCHING CONTROLLER, 1180 kHz SWITCHING FREQ-MAX, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 503K |
| 代理商： | 5962-8768105VEA |
DESCRIPTION (CONTINUED)
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV
NI
EAOUT
CLK/LEB
RT
CT
RAMP
SS
VREF
VCC
OUTB
VC
PGND
OUTA
GND
ILIM
J PACKAGE
(TOP VIEW)
SLUS873A – JANUARY 2009 – REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com
This device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Functional improvements have also been implemented in this family. The UC1825 shutdown comparator is now
a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that
ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs
are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to
insure that the fault frequency does not exceed the designed soft start period. The UC1825 CLOCK pin has
become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and
has been buffered for easier interfacing.
The UC1825A has dual alternating outputs and the same pin configuration of the UC1825. A version parts have
UVLO thresholds identical to the original UC1825.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–55°C to 125°C
CDIP-16
5962-8768105VEA
UC1825AJ-SP
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
THERMAL INFORMATION
PACKAGE
θ
JA
θ
JC
J-16
80-120
28(1)
(1)
θJC data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states, "The baseline values shown are worst case (mean
+ 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 square mils. For device die
size greater than 14400 square mils use the following values; dual-in-line, 11°C/W; flat pack, 10°C/W; pin grid array, 10°C/W".
2
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): UC1825A-SP
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