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| 型號(hào)： | 5962-0520601VZC |
| 元件分類： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 7/42頁 |
| 文件大?。?/td> | 1310K |
| 代理商： | 5962-0520601VZC |
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Symbol
Parameters
Conditions
Notes
Typical
(Note 7)
Units
t
CalDly
Calibration delay determined by pin
127 Low
See Section 1.1.1, Figure 9
(Note 10)
225
Clock Cycles
(min)
t
CalDly
Calibration delay determined by pin
127 High
See Section 1.1.1, Figure 9
(Note 10)
231
Clock Cycles
(max)
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2:
All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3:
When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than V
A), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two. This limit is not placed upon the power, ground and digital output pins.
Note 4:
Human body model is 100 pF capacitor discharged through a 1.5 k
resistor.
Note 5:
The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
20180204
Note 6:
To guarantee accuracy, it is required that V
A and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
achieving rated performance requires that the bottom be well grounded.
Note 7:
Typical figures are at T
A = 25°C, and represent most likely parametric norms.
Note 8:
Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see
Specification Definitions for Gain Error.
Note 9:
The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to
ground are isolated from the die capacitances by lead and bond wire inductances.
Note 10:
This parameter is guaranteed by design and is not tested in production.
Note 11:
This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 12:
The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 13:
Each of the two converters of the ADC08D1000 has two LVDS output buses, which each clock data out at one half the sample rate. The data at each
bus is clocked out at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one Input Clock cycle less than the latency of the
first bus (Dd0 through Dd7).
Note 14:
Tying V
BG to the supply rail will increase the output offset voltage (VOS) by 330mv (typical), as shown in the VOS specification above. Tying VBG to the
supply rail will also affect the differential LVDS output voltage (V
OD), causing it to increase by 40mV (typical).
15
www.national.com
ADC08D1000QML
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| 5962-0520801QXC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Rad Hard 512K x 8 5V Tolerant Very Low Power CMOS SRAM |
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