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參數(shù)資料
| 型號(hào)： | 5962-0520601VZC |
| 元件分類： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 32/42頁 |
| 文件大?。?/td> | 1310K |
| 代理商： | 5962-0520601VZC |
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power consumption is still high enough to require attention to
thermal management. For reliability reasons, the die temper-
ature should be kept to a maximum of 150°C. That is, T
A
(ambient temperature) plus ADC power consumption times
θ
JA (junction to ambient thermal resistance) should not ex-
ceed 150°C.
Please note the following recommendations for mounting this
device onto a PCB. This should be considered the starting
point in PCB and assembly process development. It is rec-
ommended that the process be developed based upon past
experience in package mounting.
The bottom of the package of the ADC08D1000 provides the
primary heat removal path as well as excellent electrical
grounding to the printed circuit board. The land pattern design
for lead attachment to the PCB should be the same as for a
conventional LQFP, but the bottom of the package must be
attached to the board to remove the maximum amount of heat
from the package, as well as to ensure best product para-
metric performance.
To maximize the removal of heat from the package, a thermal
land pattern must be incorporated on the PC board within the
footprint of the package. The bottom of the device must be
soldered down to ensure adequate heat conduction out of the
package. The land pattern for this exposed pad should be as
large as the 600 x 600 mil bottom of the package and be lo-
cated such that the bottom of the device is entirely over that
thermal land pattern. This thermal land pattern should be
electrically connected to ground.
20180221
FIGURE 19. Recommended Package Land Pattern
Since a large aperture opening may result in poor release, the
aperture opening should be subdivided into an array of small-
er openings, similar to the land pattern of Figure 19.
To minimize junction temperature, it is recommended that a
simple heat sink be built into the PCB. This is done by includ-
ing a copper area of about 2.25 square inches (14.52 square
cm) on the opposite side of the PCB. This copper area may
be plated or solder coated to prevent corrosion, but should
not have a conformal coating, which could provide some ther-
mal insulation. Thermal vias should be used to connect these
top and bottom copper areas. These thermal vias act as "heat
pipes" to carry the thermal energy from the device side of the
board to the opposite side of the board where it can be more
effectively dissipated. The use of approximately 100 thermal
vias is recommended. Use of a higher weight if copper on the
internal ground plane is recommended, (i.e. 2
OZ instead of
1
OZ, for thermal considerations only.
The thermal vias should be placed on a 61 mil grid spacing
and have a diameter of 15 mil typically. These vias should be
barrel plated to avoid solder wicking into the vias during the
soldering process as this wicking could cause voids in the
solder between the package exposed pad and the thermal
land on the PCB. Such voids could increase the thermal re-
sistance between the device and the thermal land on the
board, which would cause the device to run hotter.
If it is desired to monitor die temperature, a temperature sen-
sor may be mounted on the heat sink area of the board near
the thermal vias. .Allow for a thermal gradient between the
temperature sensor and the ADC08D1000 die of
θ
J-PAD times
typical power consumption.
2.8 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. A single ground plane
should be used, instead of splitting the ground plane into ana-
log and digital areas.
Since digital switching transients are composed largely of
high frequency components, the skin effect tells us that total
ground plane copper weight will have little effect upon the
logic-generated noise. Total surface area is more important
than is total ground plane volume. Coupling between the typ-
ically noisy digital circuitry and the sensitive analog circuitry
can lead to poor performance that may seem impossible to
isolate and remedy. The solution is to keep the analog cir-
cuitry well separated from the digital circuitry.
High power digital components should not be located on or
near any linear component or power supply trace or plane that
services analog or mixed signal components as the resulting
common return current path could cause fluctuation in the
analog input “ground” return of the ADC, causing excessive
noise in the conversion result.
Generally, we assume that analog and digital lines should
cross each other at 90° to avoid getting digital noise into the
analog path. In high frequency systems, however, avoid
crossing analog and digital lines altogether. The input clock
lines should be isolated from ALL other lines, analog AND
digital. The generally accepted 90° crossing should be avoid-
ed as even a little coupling can cause problems at high
frequencies. Best performance at high frequencies is ob-
tained with a straight signal path.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. This is
especially important with the low level drive required of the
ADC08D1000. Any external component (e.g., a filter capaci-
tor) connected between the converter's input and ground
should be connected to a very clean point in the analog
ground plane. All analog circuitry (input amplifiers, filters, etc.)
should be separated from any digital components.
2.9 DYNAMIC PERFORMANCE
The ADC08D1000 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications and avoid
jitter-induced noise, the clock source driving the CLK input
must exhibit low rms jitter. The allowable jitter is a function of
the input frequency and the input signal level, as described in
Section 2.4.
It is good practice to keep the ADC input clock line as short
as possible, to keep it well away from any other signals and
to treat it as a transmission line. Other signals can introduce
jitter into the input clock signal. The clock signal can also in-
troduce noise into the analog path if not isolated from that
path.
www.national.com
38
ADC08D1000QML
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