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參數(shù)資料
| 型號： | 5962-0423502KXC |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQFP52 |
| 封裝： | 0.956 X 0.956 INCH, 0.100 INCH HEIGHT, HERMETIC SEALED, CERAMIC, QFP-52 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 259K |
| 代理商： | 5962-0423502KXC |
12
SCD5028-1 Rev J 9/30/08
Aeroflex Plainview
Reading the ACT 5028B
The Busy signal is asynchronous to the Read signal created by the interface circuit that reads it. Because of the
asynchronous nature of the system (inherent with other Resolver to Digital Converters) the designer must be careful
when reading the digital interface.
The implementation of reading the RDC is accomplished in one of two ways, using a CPU/MPU or using an FPGA.
The best method for reading the counter may also depend on the rep rate of the counter clock that can vary from 0 to
1S.
The Busy pulse is instrumental in reading stable data from the ACT5028. The Busy pulse will be present for the
following two situations:
1) When ever data is incremented or decremented in the RDC counter.
2) Directly after the trailing positive going edge of /INH (see A within example 5 timing diagram).
Based on 1 above there are many methods that can be implemented to synchronize the reading of data from the
ACT5028, below are a few examples:
Example 1: If the only time a read will occur is after the RDC has stopped (0 rps) there will be no Busy signal
to contend with.
Example 2: Knowing the Busy rep rate an Interrupt to a CPU or Logic can be developed from the Busy pulse
for the system to Read the RDC chip as long as the read is guaranteed to occur prior to the next
Busy pulse.
Example 3: As long as the resolver is rotating the Busy Pulse can be used to indicate stable data to be
sampled on leading or trailing edge.
Example 4: Ignore Busy and perform two reads back to back and compare, if they are equal you have good
data. The designer should be aware of the rep rate of Busy which is equal to the clock rate of the
counter. In most cases the angular velocity is < 3 rps in which case with a 16 bit counter rep rate
would be (1 / 216 * 3) 5S. In this situation the reads would like to be within 5s of each other
and the LSB would be ignored. Although this method would be easier to implement with a CPU
it could also be done in an FPGA.
Example 5: The circuit below ignores the Busy signal but insures sampling of stable data. The clock should
be a least 10MHz, the /RD pulse should be a minimum of 1.2s (to insure minimum /INH pulse
width of 400ns), the sampling of data should be taken on the rising edge of the signal /RD. The
/RD signal is synced up with the CLK such that the sampling on the D latch occurs on the
opposite edge of the /RD transition.
/INH & /EN
Busy
Q
/Q
D
CK
CLK
Q
/Q
D
CK
/RD
S
EXAMPLE 5 CIRCUIT
相關(guān)PDF資料 |
PDF描述 |
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| 5962-0423502KXA | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQFP52 |
| 5962-0423502KXA | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQFP52 |
| 5962-0423502KXC | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQFP52 |
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| 5962-0423501KXC | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQFP52 |
相關(guān)代理商/技術(shù)參數(shù) |
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| 5962-0423801KXA | 制造商:International Rectifier 功能描述:Module DC-DC 1-OUT 3.3V 3.03A 10W 7-Pin Case S 制造商:International Rectifier 功能描述:SINGLE CHANNEL 3.3 VOLT - Bulk |
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