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參數(shù)資料
| 型號： | 5962-0423502KXC |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQFP52 |
| 封裝： | 0.956 X 0.956 INCH, 0.100 INCH HEIGHT, HERMETIC SEALED, CERAMIC, QFP-52 |
| 文件頁數(shù)： | 20/23頁 |
| 文件大?。?/td> | 259K |
| 代理商： | 5962-0423502KXC |
6
SCD5028-1 Rev J 9/30/08
Aeroflex Plainview
TIMING SPECIFICATIONS 6
(TA = 25°C with 50pf Load)
DIGITAL OUTPUT – Rise Time / Fall Time
SYM
COMMENTS
MIN
TYP2
MAX
UNITS
Busy
tLH
Rise Time
-20
85
ns
tHL
Fall Time
-20
85
ns
CW/CCW, Ripple, B1- B16
tLH
Rise Time
-
45
100
ns
tHL
Fall Time
-
45
100
ns
Busy Pulse Width
tBPW
300
400
600
ns
Busy to Data Stable
tBDS
Enable = Low
-
350
ns
Ripple Pulse Width
tRPW
160
200
300
ns
Busy to Ripple
tBR
-
100
150
ns
READ DATA – Enable & INH would normally be tied together, Data Load = Logic Hi
Enable Low to Data Stable
tELDS
--
70
ns
Enable High to Data Hi-Z
tEHZ
--
70
ns
INH Low to Data Stable
tILDS
-
400
ns
INH High to Data Change
tIHZ
-
150
ns
WRITING DATA – Enable & INH = Logic Hi
Data Load Pulse Width
tDLPW
Transparent Trailing Edge
Latch
200
-
ns
Data Setup to Data Load
tWDS
60
-
ns
Data Hold
tWDH
10
-
ns
Notes
1. @ 10 Bits, FREF > 4 x BWCL
@ 12 Bits, FREF > 8 x BWCL
@ 14 Bits, FREF > 12 x BWCL
@ 16 Bits, FREF > 16 x BWCL
2. All typical values are measured at +25°C.
3. Characteristics are guaranteed by design, not production tested.
4. Accuracy apply over the full operating Power Supply voltage range, Full operating Temperature range, Reference Frequency range,
10% Signal Amplitude variation and 10% Reference Harmonic distortion.
5. For ESD protection the ACT5028B features limiting resistors in series with diodes. Proper ESD precautions are strongly
recommended to avoid functional damage or performance degradation.
6. All testing at nominal voltage.
7. All unused inputs shall be tied to Ground. Bit 1 is always the MSB.
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| 5962-0423502KXA | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQFP52 |
| 5962-0423502KXA | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQFP52 |
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