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參數(shù)資料
| 型號： | 571MDAFREQDG |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 10 MHz - 945 MHz, LVPECL OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-8 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 315K |
| 代理商： | 571MDAFREQDG |
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Si570/Si571
12
Rev. 0.31
3. Functional Description
The Si570 XO and the Si571 VCXO are low-jitter,
programmable oscillators ideally suited for applications
requiring multiple frequencies. The Si57x can be
programmed to generate any output clock rate between
10 and 1.4 GHz with <1 ppb resolution. Output jitter
performance exceeds the strict requirements of high-
speed communication systems including OC-48/OC-
192 and 10 Gigabit Ethernet.
The
Si57x
employs
Silicon
Laboratories’
third-
generation digital signal processing based phase-
locked loop (DSPLL) technology providing excellent
jitter performance, digital programmability, and stability
while requiring minimal external components. At the
core of the Si57x is a digitally-controlled oscillator
(DCO) based on DSPLL technology that is driven by a
digital frequency control word and produces a low-jitter
output clock. (See "1. Detailed Block Diagrams" on
3.1. Frequency Programming Summary
The output frequency is determined by programming
the output dividers (HS_DIV and N1) and the fine
frequency
control
value
(RFREQ).
The
value
programmed into RFREQ is a high-resolution 38-bit
value that adjusts the DCO frequency in a range from
4.85 to 5.67 GHz. The output of the DCO is divided
down by HS_DIV and N1 to produce the desired output
frequency. The 38-bit length of RFREQ provides an
output frequency resolution of better than 1 ppb.
3.2. Frequency Programming Details
Programming consists of the following basic steps:
deriving the actual crystal frequency, choosing new
output dividers (HS_DIV & N1), calculating a new
frequency multiplier (RFREQ), and writing the new
frequency set into the device (HS_DIV, N1, and
RFREQ).
3.2.1. Selecting the Correct Output Dividers
By listing all of the combinations of HS_DIV and N1,
one can choose the output divider set with the lowest
power within the allowed internal oscillator frequency
range as specified in Table 12. The sets of dividers
should be sorted to minimize fosc for power dissipation
and to minimize N1 divider's power consumption.
Silicon Laboratories’ Si57x software automatically
provides this optimization and returns the smallest
HS_DIV x N1 combination with the highest HS_DIV
value.
3.2.2. Calculating the Reference Frequency Multi-
plier (RFREQ)
RFREQ is a binary representation of the reference
frequency multiplier and is 38 bits in length. To convert
from a decimal number to the binary number RFREQ
must be broken into two parts: the integer portion and
the fractional portion. The first 10 most-significant-bits
(MSBs) of RFREQ represent the integer portion, and
the lower 28 least-significant-bits (LSB's) represent the
fractional portion. The integer portion can be converted
directly
from
decimal
to
binary
(e.g.
decimal
43 = hexadecimal
02Bh--the
leading
nibble
only
occupies two bits of RFREQ). The fractional portion
should be made into an integer by multiplying by 228
and truncating (or rounding) the result as follows:
(e.g. 0.54587216*2^28 = 146531442.18730496; then,
truncate to 146531442). The truncated value can then
be
converted
to
binary
(e.g.
decimal
146531442 = hexadecimal 8BBE472h). The resulting
binary RFREQ for 43.54587216 is 02B8BBE472h
(02Bh concatenated with 8BBE472h).
3.2.3. Programming Procedure
The following steps must be followed to set a new
output frequency:
1. Read the frequency configuration (RFREQ, HS_DIV,
and N1) from the device after power-up or reset.
2. Calculate the actual nominal crystal frequency
(fXTAL) as: (fXTAL =f0 x HS_DIV x N1)/RFREQ
where f0 is the nominal output frequency.
3. Choose new output frequency (f1).
4. Choose the output dividers (HS_DIV and N1) for the
new output frequency by ensuring the DCO
oscillation frequency (fosc) is within the allowed
internal oscillator frequency (See Table 12) where:
fosc =f1 xHS_DIVx N1.
5. Calculate the new crystal frequency multiplication
ratio (RFREQ1) as: fosc =fXTAL xRFREQ.
6. Freeze the DCO (bit 4 of Register 137).
7. Write the frequency configuration (RFREQ, HS_DIV,
and N1).
8. Unfreeze the DCO and assert the NewFreq bit (bit 6
of Register 135) within the maximum delay specified
3.2.4. Programming Procedure Example
The Si57x-EVB software can be used to generate
examples as needed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 571MDB000105DG | 功能描述:VCXO振蕩器 Prgramble VCXO 8pin 7mmx5mm RoHS:否 制造商:Fox 封裝 / 箱體:5 mm x 3.2 mm 頻率:19.2 Mhz 頻率穩(wěn)定性:2.5 PPM 輸出格式: 封裝:Reel 電源電壓:3 V 端接類型:SMD/SMT 尺寸:3.2 mm W x 5 mm L x 1.5 mm H 最小工作溫度:- 20 C 最大工作溫度:+ 75 C |
| 571MDB000105DGR | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ VCXO LVPECL 8SMD - Tape and Reel |
| 571MEA000107DG | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays |
| 571MEA000122DG | 制造商:Silicon Laboratories Inc 功能描述:CONTROLLED OSCILLATOR 1GHZ VCXO LVPECL 6-PIN SMD - Trays |
| 571MEB000105DG | 功能描述:VCXO振蕩器 Prgramble VCXO 8pin 7mmx5mm RoHS:否 制造商:Fox 封裝 / 箱體:5 mm x 3.2 mm 頻率:19.2 Mhz 頻率穩(wěn)定性:2.5 PPM 輸出格式: 封裝:Reel 電源電壓:3 V 端接類型:SMD/SMT 尺寸:3.2 mm W x 5 mm L x 1.5 mm H 最小工作溫度:- 20 C 最大工作溫度:+ 75 C |
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