參數(shù)資料
型號: 558G-01LF
英文描述: PECL/CMOS TO CMOS CLOCK DIVIDER
中文描述: PECL的/ CMOS半導(dǎo)體技術(shù)的CMOS時鐘分頻器
文件頁數(shù): 2/5頁
文件大小: 88K
代理商: 558G-01LF
PECL/CMOS
TO
CMOS C
LOCK
D
IVIDER
MDS 558-01 C
2
Revision 122105
Integrated Circuit Systems
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS558-01
Pin Assignment
Input Clock Selection
Tri-State Table
Output Divide Selection
Pin Descriptions
12
1
11
2
10
3
9
S0
4
S1
5
VDDP
6
VDDC
7
PECLIN
8
PECLIN
CLK1
CLK2
CLK3
GND
CLK4
OE1
CMOSIN
GND
16
15
14
13
OE0
SELPECL
16-pin 173 Mil (0.65mm) TSSOP
SELPECL
Input
0
CMOSIN
1
PECLIN
OE1
OE0
CLK 1
CLK 2, 3, 4
0
0
Tri-state
Tri-state
0
1
Clock ON
Tri-state
1
0
Tri-state
Clock ON
1
1
Clock ON
Clock ON
S1
S0
Output Divide
0
0
/1
0
1
/2
1
0
/3
1
1
/4
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
S0
S1
VDDP
PECLIN
PECLIN
GND
CMOSIN
OE0
OE1
GND
CLK4
CLK3
CLK2
CLK1
VDDC
SELPECL
Pin Type
Pin Description
Input
Input
Power
Clock Input
Clock Input
Power
Clock Input
Input
Input
Power
Output
Output
Output
Output
Power
Input
Select 0 for output divider. See table above. Internal pull-up to VDDP.
Select 1 for output divider. See table above. Internal pull-up to VDDP.
Connect to +3.3 V or +5 V. Decouple to pin 6.
PECL input. Connect to ground if not used.
Complimentary PECL input. Connect to ground if not used.
Connect to ground.
CMOS input. Connect to ground if not used.
Output Enable 0. See table above. Internal pull-up to VDDP.
Output Enable 1. See table above. Internal pull-up to VDDP.
Connect to ground.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Connect to +2.5 V, +3.3 V, or +5 V. Decouple to pin 10.
Selects PECL or CMOS input. See table above. Internal pull-up to
VDDP.
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