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參數資料
| 型號： | 54F632 |
| 英文描述： | 32-Bit Parallel Error Detection and Correction Circuit |
| 中文描述： | 32位并行錯誤檢測和校正電路 |
| 文件頁數： | 7/14頁 |
| 文件大?。?/td> | 225K |
| 代理商： | 54F632 |
Functional Description
(Continued)
TABLE VI. Read-Modify-Write Function
Memory
Cycle
EDAC
Function
Control
S
1
DB Output
Latch
LEDBO
CB
Error Flags
ERR
S
0
BYTEn
*
OEBn
*
Check I/O
Control
OECB
MERR
Read
Read & Flag
H
L
Input
H
X
Input
H
Enabled
Read
Latch Input
Data &
Check Bits
Latched
Input
Data
Latched
Input
Check Word
H
H
H
L
H
Enabled
Read
Latch Corrected
Data Word into
Output Latch
Latched
Output
Data
Word
High Z
H
H
H
H
H
Output
Syndrome
Bits
L
Enabled
Modify/
Write
Modify
Appropriate
Byte or Bytes
& Generate New
Check Word
Input
Modified
BYTE
0
H
L
L
H
Output
Check Word
L
H
H
Output
Unchanged
BYTE
0
L
*
OEB
0
controls DB
0
–DB
7
(BYTE
0
); OEB
1
controls DB
8
–DB
15
(BYTE
1
); OEB
2
controls DB
16
–DB
23
(BYTE
2
); OEB
3
controls DB
24
–DB
31
(BYTE
3
).
TABLE VII. Diagnostic Function
EDAC
Function
Control
S
1
DB Byte
Control
OEB
n
DB Output
Latch
LEDBO
CB
Error Flags
ERR
S
0
Data I/O
Check I/O
Control
OECB
MERR
Read & Flag
H
L
Input Correct
Data Word
H
X
Input Correct
Check Bits
H
H
Latch Input Check
Word while Data
Input Latch
Remains
Transparent
Input
Diagnostic
Data Word
*
Latched
Input
Check Bits
L
H
H
L
H
Enabled
Latch Diagnostic
Data Word into
Output Latch
Input
Diagnostic
Data Word
Output
Latched
Check Bits
L
H
H
H
L
Enabled
High Z
H
Latch Diagnostic
Data Word into
Input Latch
Latched
Input
Diagnostic
Data Word
Output
Syndrome
Bits
H
H
H
H
L
Enabled
High Z
H
Output Diagnostic
Data Word &
Syndrome Bits
Output
Diagnostic
Data Word
Output
Syndrome
Bits
H
H
L
H
L
Enabled
High Z
H
Output Corrected
Diagnostic Data
Word & Output
Syndrome Bits
Output
Corrected
Diagnostic
Data Word
Output
Syndrome
Bits
H
H
L
L
L
Enabled
High Z
H
*
Diagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case,the diagnostic data word will contain errors in
two bit locations.
7
相關PDF資料 |
PDF描述 |
|---|---|
| 54F632DM | Error Detection & Correction (EDAC) |
| 54F632DMQB | Error Detection & Correction (EDAC) |
| 54F632DMQR | Error Detection & Correction (EDAC) |
| 54F632LM | Error Detection & Correction (EDAC) |
| 74F640 | Octal bus transceiver, inverting (3-State)(八通道總線收發(fā)器，反向（三態(tài)）) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 54F632DM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Error Detection & Correction (EDAC) |
| 54F632DMQB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Error Detection & Correction (EDAC) |
| 54F632DMQR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Error Detection & Correction (EDAC) |
| 54F632LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Error Detection & Correction (EDAC) |
| 54F64 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4-2-3-2-Input AND-OR-Invert Gate |
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