- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360441 > 54F632 32-Bit Parallel Error Detection and Correction Circuit PDF資料下載
參數(shù)資料
| 型號： | 54F632 |
| 英文描述： | 32-Bit Parallel Error Detection and Correction Circuit |
| 中文描述： | 32位并行錯誤檢測和校正電路 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 225K |
| 代理商： | 54F632 |
Functional Description
(Continued)
TABLE IV. Read, Flag and Correct Function
Memory
Cycle
EDAC
Function
Control
S
1
DB Control
OEB
n
DB Output
Latch
LEDBO
CB
Error Flags
ERR
S
0
Data I/O
Check I/O
Control
OECB
MERR
Read
Read & Flag
H
L
Input
H
X
Input
H
Enabled (Note 1)
Read
Latch Input
Data & Check
Bits
Latched
Input
Data
Latched
Input
Check Word
H
H
H
L
H
Enabled (Note 1)
Read
Output
Corrected Data
& Syndrome Bits
Output
Corrected
Data Word
Output
Syndrome
Bits (Note 2)
H
H
L
X
L
Enabled (Note 1)
Note 1:
See Table III for error description.
Note 2:
See Table V for error location.
TABLE V. Syndrome Decoding
Syndrome Bits
Error
6
5
4
3
2
1
0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
unc
2-Bit
2-Bit
unc
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
2-Bit
unc
unc
2-Bit (Note 2)
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
2-Bit
unc
DB
31
2-Bit
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
unc
2-Bit
2-Bit
DB
30
2-Bit
unc
DB
29
2-Bit
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
DB
28
2-Bit
2-Bit
DB
27
DB
26
2-Bit
2-Bit
DB
25
2-Bit
DB
24
unc
2-Bit
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
Syndrome Bits
Error
6
5
4
3
2
1
0
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
2-Bit
unc
DB
7
2-Bit
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
DB
6
2-Bit
2-Bit
DB
5
DB
4
2-Bit
2-Bit
DB
3
2-Bit
DB
2
unc
2-Bit
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
DB
0
2-Bit
2-Bit
unc
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
2-Bit
DB
1
unc
2-Bit
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
2-Bit
unc
unc
2-Bit
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
unc
2-bit
2-bit
CB
6
CB
X
e
Error in check bit X
DB
Y
e
Error in data bit Y
2-Bit
e
Double-bit error
unc
e
Uncorrectable multi-bit error
Note:
2-bit and unc condition will cause both ERR and MERR to be LOW
Note 1:
Syndrome bits for all LOWs. MERR and ERR LOW for all LOWs,
only ERR LOW for DB
30
error.
Note 2:
Syndrome bits for all HIGHs.
5
相關PDF資料 |
PDF描述 |
|---|---|
| 54F632DM | Error Detection & Correction (EDAC) |
| 54F632DMQB | Error Detection & Correction (EDAC) |
| 54F632DMQR | Error Detection & Correction (EDAC) |
| 54F632LM | Error Detection & Correction (EDAC) |
| 74F640 | Octal bus transceiver, inverting (3-State)(八通道總線收發(fā)器，反向（三態(tài)）) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 54F632DM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Error Detection & Correction (EDAC) |
| 54F632DMQB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Error Detection & Correction (EDAC) |
| 54F632DMQR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Error Detection & Correction (EDAC) |
| 54F632LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Error Detection & Correction (EDAC) |
| 54F64 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4-2-3-2-Input AND-OR-Invert Gate |
發(fā)布緊急采購，3分鐘左右您將得到回復。