參數(shù)資料
型號(hào)： 522932B
英文描述： Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits
中文描述： 集成電路
文件頁(yè)數(shù)： 12/16頁(yè)
文件大?。?/td> 141K
代理商： 522932B
12
LTC 690/LTC 691
LTC 694/LTC 695
Watchdog Timer
The LTC690 family provides a watchdog timer function to
monitor the activity of the microprocessor. If the micro-
processor does not toggle the Watchdog Input (WDI)
within a seleced time-out period, RESET is forced to active
low for a minimum of 35ms for the LTC690/LTC691
(140ms for the LTC694/LTC695). The reset active time is
adjustable on the LTC691/LTC695. Since many systems
can not service the watchdog timer immediately after a
reset, the LTC691 and LTC695 have longer time-out
period (1.0 second minimum) right after a reset is issued.
The normal time-out period (70ms minimum) becomes
effective following the first transition of WDI after RESET
is inactive. The watchdog time-out period is fixed at 1.0
second minimum on the LTC690 and LTC694. Figure 11
shows the timing diagram of watchdog time-out period
and reset active time. The watchdog time-out period is
restarted as soon as RESET is inactive. When either a high-
to-low or low-to-high transition occurs at the WDI pin
prior to time-out, the watchdog time is reset and begins to
time out again. To ensure the watchdog time does not time
out, either a high-to-low or low-to-high transition on the
WDI pin must occur at or less than the minimum time-out
period. If the input to the WDI pin remains either high or
low, reset pulses will be issued every 1.6 seconds typi-
cally. The watchdog time can be deactivated by floating the
WDI pin. The timer is also disabled when V
CC
falls below
the reset voltage threshold or V
BATT
.
U
S
A
of LT1086-5 (4.75V + 1.5V) and V
HYSTERESIS
= 850mV.
O
PPLICATI
U
U
The 10.7ms allows enough time to execute shutdown
procedure for microprocessor and 831mV of hysteresis
would prevent PFO from going low due to the noise of V
IN
.
Example 2:
The circuit in Figure 9 can be used to measure
the regulated 5V supply to provide early warning of power
failure. Because of variations in the PFI threshold, this
circuit requires adjustment to ensure the PFI comparator
trips before the reset threshold is reached. Adjust R5 such
that the PFO output goes low when the V
CC
supply reaches
the desired level (e.g., 4.85V).
Monitoring the Status of the Battery
C3 can also monitor the status of the memory back-up
battery (Figure 10). If desired, the CE OUT can be used to
apply a test load to the battery. Since CE OUT is forced high
in battery back-up mode, the test load will not be applied
to the battery while it is in use, even if the microprocessor
is not powered.
V
5VR1
R3
850V
HYSTERESIS
=
=
R3
≈
5.88 R1
(7.32V ±6.25V)
100mV/ms
V
HYSTERESIS
= 8.151V – 7.32V = 831mV
10.7ms
=
V
1.3V 1
51k
10k
51k
300k
8.151V
H
=
+
+
=
Choose R3 = 300k and R1 = 51k. Also select R4 = 10k
which is much smaller than R3.
R2 = 9.7k
, Choose nearest 5% resistor 10k and recalcu-
late V
L
,
7.5V =1.3V 1+R2±(5V±1.3V)51
13 310
k
k
k
V
1.3V 1
1.3V(310k
L
=
+
=
10k±(5V ±1.3V)51
732
.
k
)
V
3V
5V
690 F10
R1
1M
R
L
20K
R2
1M
OPTIONAL TEST LOAD
LOW-BATTERY SIGNAL
TO
μ
P I/O PIN
I/O PIN
V
CC
V
BATT
GND
PFI
LTC691
LTC695
CE IN
PFO
CE OUT
Figure 10. Back-Up Battery Monitor with Optional Test Load
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