參數(shù)資料
型號(hào)： 514SCCXXXXXXAAG
廠商： SILICON LABORATORIES
元件分類： XO, clock
英文描述： 125 MHz, OTHER CLOCK GENERATOR, PDSO6
封裝： 5 X 7 MM, ROHS COMPILANT PACKAGE-6
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 267K
代理商： 514SCCXXXXXXAAG
Si514
22
Preliminary Rev. 0.9
4.3. I2C Interface
Configuration and operation of the Si514 is controlled by reading and writing to the RAM space using the I2C
interface. The device operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps)
or Fast-Mode (400 kbps). Burst data transfer with auto address increments are also supported.
The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both the SDA and SCL
pins must be connected to the VDD supply via an external pull-up as recommended by the I2C specification. The
Si514 7-bit I2C slave address is user-customized during the part number configuration process. See "5. Pin
Descriptions" on page 24 for more details.
Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7-
bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 5.
A write burst operation is also shown where every additional data word is written using an auto-incremented
address.
Figure 5. I2C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
From slave to master
From master to slave
Write Operation – Single Byte
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A
Data [7:0]
P
A
Write Operation - Burst (Auto Address Increment)
Reg Addr +1
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A
Data [7:0]
A
Data [7:0]
P
A
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