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參數(shù)資料
| 型號(hào)： | 505892X |
| 英文描述： | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 中文描述： | 集成電路 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 278K |
| 代理商： | 505892X |
9
LT1083/LT1084/LT1085
APPLICATIO
S I
N
FOR
ATIO
U
The problem occurs with a heavy output load when the
input voltage is high and the output voltage is low, such as
immediately after removal of a short. The load line for such
a load may intersect the output current curve at two points.
If this happens, there are two stable output operating
points for the regulator. With this double intersection, the
power supply may need to be cycled down to zero and
brought up again to make the output recover.
W
U
Ripple Rejection
The typical curves for ripple rejection reflect values for a
bypassed adjustment pin. This curve will be true for all
values of output voltage. For proper bypassing and ripple
rejection approaching the values shown, the impedance of
the adjust pin capacitor at the ripple frequency should be
less than the value of R1, (normally 100
to 120
). The
size of the required adjust pin capacitor is a function of the
input ripple frequency. At 120Hz the adjust pin capacitor
should be 25
μ
F if R1 = 100
. At 10kHz only 0.22
μ
F is
needed.
For circuits without an adjust pin bypass capacitor, the
ripple rejection will be a function of output voltage. The
output ripple will increase directly as a ratio of the output
voltage to the reference voltage (V
OUT
/V
REF
). For example,
with the output voltage equal to 5V and no adjust pin
capacitor, the output ripple will be higher by the ratio of 5V/
1.25V or four times larger. Ripple rejection will be de-
graded by 12dB from the value shown on the typical curve.
Output Voltage
The LT1083 develops a 1.25V reference voltage between
the output and the adjust terminal (see Figure 1). By
placing a resistor R1 between these two terminals, a
constant current is caused to flow through R1 and down
through R2 to set the overall output voltage. Normally this
current is the specified minimum load current of 10mA.
Because I
ADJ
is very small and constant when compared
with the current through R1, it represents a small error and
can usually be ignored.
Figure 1. Basic Adjustable Regulator
R1
R2
IN
OUT
I
ADJ
50
A
ADJ
V
OUT
LT1083
V
IN
1083/4/5 ADJ F01
V
REF
V
OUT
= V
REF
1 + R1
ADJ
R2
(
)
Load Regulation
Because the LT1083 is a three-terminal device, it is not
possible to provide true remote load sensing. Load regu-
lation will be limited by the resistance of the wire connect-
ing the regulator to the load. The data sheet specification
for load regulation is measured at the bottom of the
package. Negative side sensing is a true Kelvin connec-
tion, with the bottom of the output divider returned to the
negative side of the load. Although it may not be immedi-
ately obvious, best load regulation is obtained when the
top of the resistor divider R1 is connected directlyto the
case not to the load This is illustrated in Figure 2. If R1
were connected to the load, the effective resistance be-
tween the regulator and the load would be:
R
R
R
R
R
Parasitic Line
P
P
×
+
=
2
1
1
,
Resistance
Figure 2. Connections for Best Load Regulation
LT1083
OUT
IN
V
IN
ADJ
R
PARASITIC
LINE RESISTANCE
R1*
*CONNECT R1 TO CASE
CONNECT R2 TO LOAD
1083/4/5 ADJ F02
R
L
R2*
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