參數(shù)資料
型號(hào)： 403GCX-3BC80C2A
元件分類： 復(fù)位半導(dǎo)體
英文描述： 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述： 32位微處理器
文件頁(yè)數(shù)： 24/48頁(yè)
文件大?。?/td> 768K
代理商： 403GCX-3BC80C2A
IBM PowerPC 403GC
24
Note:
1. Output times are measured with a standard 50 pF capacitive load, unless otherwise noted.
Input Setup and Hold Waveform
Notes:
1. The 403GC may be programmed to latch data from the data bus either on the rise of SysClk or the rise of CAS.
When the 403GC is programmed to latch data on CAS, bit 26 of the I/O control register (IOCR) is set to 1.
2. T
CAS2CLK
≥
15.5 ns. The capacitive load on the CAS outputs must not delay the CAS low-to-high transition such
that the period from the CAS rising edge to the next SysClk rising edge becomes less than 15.5 ns. The maximum
value of CAS capacitive loading can be determined by using the output time for CAS from Table 17 on page 27,
and applying the appropriate derating factor for your application. See the figure, "Output Derating for Capacitance
and Voltage," on page 28.
Table 14. 403GC Serial Port Output Timings
Symbol
Parameter
25 MHz
33 MHz
40 MHz
Units
T
OHMin
T
OVMax
T
OHMin
T
OVMax
T
OHMin
T
OVMax
T
OH
,
T
OV
Output hold, output valid time
T
OH1
,
T
OV1
DTR/RTS
T
OH2
,
T
OV2
XmitD
14
12
13
11
12
10
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
403GCX-3JC50C2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
403GCX-3JC66C2 制造商:AppliedMicro 功能描述:
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403GCX-3JC80C2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
403GCX-3JC80C2A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
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