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參數(shù)資料
| 型號： | 403GCX-3BC80C2A |
| 元件分類： | 復(fù)位半導(dǎo)體 |
| 英文描述： | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 11/48頁 |
| 文件大?。?/td> | 768K |
| 代理商： | 403GCX-3BC80C2A |
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IBM PowerPC 403GC
11
D22
71
M10
I/O
Data bus bit 22.
D23
72
N10
I/O
Data bus bit 23.
D24
73
L10
I/O
Data bus bit 24.
D25
74
P11
I/O
Data bus bit 25.
D26
75
M11
I/O
Data bus bit 26.
D27
76
N11
I/O
Data bus bit 27.
D28
77
P12
I/O
Data bus bit 28.
D29
78
M12
I/O
Data bus bit 29.
D30
79
N12
I/O
Data bus bit 30.
D31
82
N13
I/O
Data bus bit 31.
DMAA0
156 B4
O
DMA Channel 0 Acknowledge. DMAA0 has an active level when a
transaction is taking place between the 403GC and a peripheral.
DMAA1
157 A3
O
DMA Channel 1 Acknowledge. See description of DMAA0.
DMAA2
158 C3
O
DMA Channel 2 Acknowledge. See description of DMAA0.
DMAA3/
XACK
159 B3
O
DMA Channel 3 Acknowledge / External Master Transfer Acknowl-
edge. When the 403GC is bus master, this signal is DMAA3; see
description of DMAA0. When the 403GC is not the bus master, this
signal is XACK, an output from the 403GC which has an active level
when data is valid during an external bus master transaction.
DMAR0
2
B2
I
DMA Channel 0 Request. External devices request a DMA transfer
on channel 0 by putting a logic 0 on DMAR0.
DMAR1
3
B1
I
DMA Channel 1 Request. See description of DMAR0.
DMAR2
4
C2
I
DMA Channel 2 Request. See description of DMAR0.
DMAR3/
XREQ
5
C1
I
DMA Channel 3 Request. When the 403GC is the bus master, exter-
nal devices request a DMA transfer on channel 3 by putting a logic 0
on DMAR3. See description of DMAR0.
When the 403GC is not the bus master, DMAR3 is used as the
XREQ input. The external bus master places a logic 0 on XREQ to
initiate a transfer to the DRAM controlled by the 403GC DRAM con-
troller.
DRAMOE
137 D9
O
DRAM Output Enable. DRAMOE has an active level when either the
403GC or an external bus master is reading from a DRAM bank.
This signal enables the selected DRAM bank to drive the data bus.
DRAMWE
138 B8
O
DRAM Write Enable. DRAMWE has an active level when either the
403GC or an external bus master is writing to a DRAM bank.
Table 4. 403GC Signal Descriptions
Signal
Name
Pin
Ball
I/O
Type
Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 403GCX-3JC50C2 | 32-Bit Microprocessor |
| 403GCX-3JC66C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3JC76C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3JC80C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3JC80C2A | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 403GCX-3JC50C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3JC66C2 | 制造商:AppliedMicro 功能描述: |
| 403GCX-3JC76C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3JC80C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3JC80C2A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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