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參數(shù)資料
| 型號： | 4036FY5 |
| 元件分類： | 復位半導體 |
| 英文描述： | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 中文描述： | 4036系列數(shù)據(jù)表|射頻調諧器模塊： |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 425K |
| 代理商： | 4036FY5 |
4036 FY5 RF F
RONTEND
M
ODULE
3
X
1981, 3
X
1223, 3
X
7686
D
ATA
S
HEET
PC/TV M
ULTIMEDIA
A
PPLICATIONS
3X 1981ED Revision: 03
May 01
Page 9 of 16
1981_03.DOC
P
8.2
READ DATA FORMAT
Table 12
Read Data Format
MSB
LSB
Address Byte
1
1
0
0
0
MA1
MA0
R/W
A
Status Byte
POR
FL
I2
I1
I0
A2
A1
A0
A
Table 13
Read Data Format Descriptions
C
ODE
D
ESCRIPTION
R/W
1 = Read mode
POR
Power on reset flag ( POR =1 at power on)
FL
In lock flag (FL= 1 when PLL is locked)
I2, I1, I0
Digital levels for I/O ports P7, P5 and P4 (not used)
A2, A1, A0
Digital output of 5-level ADC for AFC function. Value for
correct tuning: A2 = 0, A1= 1, A0 = 0
Note:
Short circuit at pins 18, 19, or 21 can damage internal circuits.
9
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
WARNING:
The 4036 FY5 RF Frontend Module contains components that
can be damaged by electrostatic discharge.
Observe these precautions:
Ground yourself before handling the Frontend.
Do not touch the Frontend′s connector pins without ESD protection.
10
NTSC M/N AIR
Table 14
NTSC M/N Air
R
ECEPTION
F
REQUENCY
I
2
C B
US
C
ODE
(
HEX
)
f step = 62.5 kHz
f step = 50 kHz
Control byte
Divider byte
Control byte
Divider byte
Air
channel
CH#
Pix
carrier
(MHz)
Band
1
2
1
2
1
2
1
2
2
2
55.25
VHF Low
8E
A2
06
50
88
A2
07
E4
3
3
61.25
VHF Low
8E
A2
06
B0
88
A2
08
5C
4
4
67.25
VHF Low
8E
A2
07
10
88
A2
08
D4
5
5
77.25
VHF Low
8E
A2
07
B0
88
A2
09
9C
6
6
83.25
VHF Low
8E
A2
08
10
88
A2
0A
14
7
7
175.25
VHF High
8E
94
0D
D0
88
94
11
44
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