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參數(shù)資料
| 型號(hào)： | 3D7502-40 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MONOLITHIC MANCHESTER DECODER |
| 中文描述： | 整裝曼徹斯特解碼器 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 38K |
| 代理商： | 3D7502-40 |
3D7502
Doc #97032
5/19/97
DATA DELAY DEVICES, INC.
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
The 3D7502 Manchester Decoder samples the
input at precise pre-selected intervals to retrieve
the data and to recover the clock from the
received data stream. Its architecture comprises
finely tuned delay elements and proprietary
circuitry which, in conjunction with other circuits,
implement the data decoding and clock recovery
function.
INPUT SIGNAL CHARACTERISTICS
Encoded data transmitted from a source arrives
at its destination corrupted. Such corruption of
the received data manifests itself as jitter and/or
pulse width distortion at the input to the device.
The instantaneous deviations from nominal Baud
Rate and/or Pulse Width (high or low) adversely
impact the data extraction and clock recovery
function if their published limits are exceeded.
See Table 4, Allowed Baud Rate/Duty Cycle.
The 3D7502 Manchester Decoder Data Input
is
TTL compatible. The user should assure
himself that
the 1.5 volt TTL threshold is used
when referring to all timing, especially the input
pulse widths.
FREQUENCY (JITTER) ERRORS
The 3D7502 Manchester Decoder, being a self-
timed device, is tolerant of frequency
modulation (jitter) present in the input data
stream, provided that the input data pulse width
variations remain within the allowable ranges.
OUTPUT SIGNAL CHARACTERISTICS
The 3D7502 presents at its outputs the decoded
data (inverted) and the recovered clock. The
decoded data is
valid at the rising edge of the
clock.
The clock recovery function operates in two
modes dictated by the input data stream bit
sequence. When a data bit is succeeded by its
inverse, the clock recovery circuit is engaged
and forces the clock output low for a time equal
to
one over twice the baud rate
. Otherwise,
the input is presented at the clock output
unchanged, shifted in time.
When engaged, the clock recovery circuit
generates a low-going pulse of fixed width.
Therefore, the clock duty cycle is strongly
dependent on the baud rate, as this will affect
the clock-high duration.
The clock output falling edge is not operated on
by the clock recovery circuitry. It, therefore,
preserves more accurately the clock frequency
information embedded in the transmitted data.
Therefore, it can be used, if it is desired, to
retrieve clock frequency information.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry is strongly dependent
on power supply and temperature. The
monolithic 3D7502 Manchester Decoder utilizes
novel and innovative compensation circuitry to
minimize timing variations induced by
fluctuations in power supply and/or temperature.
CLOCK
(CLK)
RECEIVED
(RX)
Figure 1: Timing Diagram
t
C
DECODED
1
0
1
1
0
0
1
ENCODED
1
0
1
1
0
0
1
0
DATA
(DATB)
t
CL
t
CWL
t
CD
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| 3D7502SERIES | MONOLITHIC MANCHESTER DECODER |
| 3D7503D-20 | MONOLITHIC MANCHESTER ENCODER/DECODER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7502-5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER DECODER |
| 3D7502-50 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER DECODER |
| 3D7502D10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7502D20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7502D25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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