參數(shù)資料
型號(hào): 3D7444-1.5
廠商: DATA DELAY DEVICES INC
元件分類(lèi): 通用總線功能
英文描述: MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444)
中文描述: SILICON DELAY LINE, TRUE OUTPUT, PDIP14
封裝: DIP-14
文件頁(yè)數(shù): 5/6頁(yè)
文件大?。?/td> 157K
代理商: 3D7444-1.5
Doc #03006
12/8/03
3D7444
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
DEVICE SPECIFICATIONS
TABLE 3: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
DC Supply Voltage
V
DD
Input Pin Voltage
V
IN
Input Pin Current
I
IN
Storage Temperature
T
STRG
Lead Temperature
T
LEAD
MIN
-0.3
-0.3
-10
-55
MAX
7.0
V
DD
+0.3
10
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 4: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
Static Supply Current*
I
DD
High Level Input Voltage
V
IH
Low Level Input Voltage
V
IL
High Level Input Current
I
IH
Low Level Input Current
I
IL
High Level Output Current
I
OH
MIN
2.0
-0.1
-0.1
TYP
1.3
0.0
0.0
-8.0
MAX
2.0
0.8
0.1
0.1
-6.0
UNITS
mA
V
V
μ
A
μ
A
mA
NOTES
V
DD
= 5.25V
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
Low Level Output Current
I
OL
6.0
7.5
mA
Output Rise & Fall Time
T
R
& T
F
2
ns
*I
(Dynamic) = 4 * C
* V
* F
where: C
LD
= Average capacitance load/line (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
TABLE 5: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
SYMBOL
MIN
T
LW
10
t
DSC
10
t
DHC
Clock Width (High or Low)
Clock Setup to Latch
Clock to Serial Output
Latch to Delay Valid
Latch to Delay Invalid
Input Pulse Width
Input Period
Period
Input to Output Delay
t
PLH
, t
PHL
PARAMETER
Latch Width
Data Setup to Clock
Data Hold from Clock
TYP
12
35
MAX
20
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
1
See Table 1
See Table 1
See Text
1
15
20
5
10
20
t
CW
t
CSL
t
PCQ
t
LDV
t
LDX
t
WI
% of Total Delay
% of Total Delay
ns
NOTES: 1 -
Refer to
PROGRAMMED DELAY (ADDRESS) UPDATE
section
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