- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358635 > 39504 (Microchip Technology Inc.) Section 4. Architecture PDF資料下載
參數(shù)資料
| 型號： | 39504 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | Section 4. Architecture |
| 中文描述： | 第4節(jié)。建筑 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 232K |
| 代理商： | 39504 |
PIC18C Reference Manual
DS39504A-page 4-6
2000 Microchip Technology Inc.
4.3
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). Fetch takes one instruction
cycle, while decode and execute takes another instruction cycle. However, due to pipelining, each
instruction effectively executes in one cycle. If an instruction causes the program counter to
change (e.g.
GOTO
instruction), then an extra cycle is required to complete the instruction (See
Example 4-1
).
The instruction
fetch
begins with the program counter incrementing in Q1.
In the
execution
cycle, the fetched instruction is latched into the “Instruction Register (IR)” in
cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data
memory is read during Q2 (operand read) and written during Q4 (destination write).
Example 4-1
shows the operation of the two stage pipeline for the instruction sequence shown.
At time T
CY
0, the first instruction is fetched from program memory. During T
CY
1, the first instruc-
tion executes, while the second instruction is fetched. During T
CY
2, the second instruction exe-
cutes, while the third instruction is fetched. During T
CY
3, the fourth instruction is fetched, while
the third instruction (
CALL SUB_1
) is executed. When the third instruction completes execution,
the CPU forces the address of instruction four onto the Stack and then changes the Program
Counter (PC) to the address of
SUB_1
. This means that the instruction that was fetched during
T
CY
3 needs to be “flushed” from the pipeline. During T
CY
4, instruction four is flushed (executed
as a
NOP
) and the instruction at address
SUB_1
is fetched. Finally during T
CY
5, instruction five is
executed and the instruction at address
SUB_1
+ 2 is fetched.
Example 4-1: Instruction Pipeline Flow
Most instructions are single cycle. Program branches take two cycles, since the fetch instruction is “flushed” from
the pipeline while the new instruction is being fetched and then executed.
T
CY
0
Fetch 1
T
CY
1
Execute 1
Fetch 2
T
CY
2
T
CY
3
T
CY
4
T
CY
5
1. MOVLW 55h
2. MOVWF PORTB
Execute 2
Fetch 3
3. CALL SUB_1
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch
SUB_1
Execute
SUB_1
Fetch
SUB_1
+ 2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 3965S-1.2 | 1.5A Ultra Low Dropout Linear Regulator |
| 39BS | surface mount silicon Zener diodes |
| 39HS | DIODE ZENER SINGLE 350mW 6.2Vz 20mA-Izt 0.05 5uA-Ir 4 SOT-23 3K/REEL |
| 39LF020 | DIODE ZENER TRIPLE ISOLATED 200mW 10Vz 20mA-Izt 0.05 3uA-Ir 8 SOT-363 3K/REEL |
| 39PS | 25PS, 42PS, 44PS, 45PS and 46PS Series Pressure Switches |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 395-0400 | 制造商:DELTRON 功能描述:PLUG INLINE 4MM GREEN |
| 3950400000 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse |
| 39504000000 | 功能描述:保險絲 125V UL FA LL .400A TE5 RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險絲類型:Fast Acting 保險絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485 |
| 395040002 | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:3.50mm (.138") Pitch Eurostyle? Horizontal Plug, with Retention Screws, 2 Circuits |
| 39504-0002 | 功能描述:可插拔接線端子 EURO 3.5MM 2 CIRCUIT HOR PLUG W/ SCREWS RoHS:否 制造商:Phoenix Contact 產(chǎn)品:Plugs 系列:PTS 端接類型:Spring Cage 位置/觸點數(shù)量:5 線規(guī)量程:26-14 節(jié)距:5 mm 電流額定值:10 A 電壓額定值:250 V 安裝風(fēng)格: 安裝角: 觸點電鍍: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。