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參數(shù)資料
| 型號(hào)： | 39504 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | Section 4. Architecture |
| 中文描述： | 第4節(jié)。建筑 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 232K |
| 代理商： | 39504 |
2000 Microchip Technology Inc.
DS39504A-page 4-3
Section 4 Architecture
A
4
Double Word Instructions:
Some operations require more information then can be stored in the 16 bits of a program memory
location. These operations require a double word instruction, and are therefore 32-bits wide.
Instructions that require this second instruction word are:
Memory to memory move instruction (12 bits for each RAM address)
-
MOVFF
SourceReg, DestReg
Literal value to FSR move instruction (12 bits for data and 2 bits for FSR to load)
-
LFSR
FSR#, Address
Call and goto operations (20 bits for address)
-
CALL
Address
-
GOTO
Address
The first word indicates to the CPU that the next program memory location is the additional infor-
mation for this instruction and not an instruction. If the CPU tries to execute the second word of
an instruction (due to a software modified PC pointing to that location as an instruction), the
fetched data is executed as a
NOP
.
Double word instruction execution is not split between the two T
CY
cycles by an interrupt request.
That is, when an interrupt request occurs during the execution of a double word instruction, the
execution of the instruction is completed before the processor vectors to the interrupt address.
The interrupt latency is preserved.
Instruction Pipeline:
The instruction pipeline is a two-stage pipeline that overlaps the fetch and execution of instruc-
tions. The fetch of the instruction takes one T
CY
, while the execution takes another T
CY
. However,
due to the overlap of the fetch of current instruction and execution of previous instruction, an
instruction is fetched and another instruction is executed every T
CY
.
Single Cycle Instructions:
With the program memory bus being 16-bits wide, the entire instruction is fetched in a single
machine cycle (T
CY
), except for double word instructions. The instruction contains all the infor-
mation required and is executed in a single cycle. There may be a one cycle delay in execution
if the result of the instruction modified the contents of the program counter. This requires the pipe-
line to be flushed and a new instruction to be fetched.
Two Cycle Instructions:
Double word instructions require two cycles to execute, since all the required information is in the
32 bits.
Reduced Instruction Set:
When an instruction set is well designed and highly orthogonal (symmetric), fewer instructions
are required to perform all needed tasks. With fewer instructions, the whole set can be more rap-
idly learned.
Register File Architecture:
The register files/data memory can be directly or indirectly addressed. All special function regis-
ters, including the program counter, are mapped in the data memory.
Orthogonal (Symmetric) Instructions:
Orthogonal instructions make it possible to carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of “special instructions” make programming
simple yet efficient. In addition, the learning curve is reduced significantly. The Enhanced MCU
instruction set uses only three non-register oriented instructions, which are used for two of the
cores features. One is the
SLEEP
instruction, which places the device into the lowest power use
mode. The second is the
CLRWDT
instruction, which verifies the chip is operating properly by pre-
venting the on-chip Watchdog Timer (WDT) from overflowing and resetting the device. The third
is the
RESET
instruction, which resets the device.
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