參數(shù)資料
型號： 3850
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 47/99頁
文件大?。?/td> 1384K
代理商： 3850
47
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. A)
Fig. 51 Internal status at reset (spec. A)
A-D control register (ADCON)
A-D conversion low-order register (ADL)
A-D conversion high-order register (ADH)
A-D input selection register (ADSEL)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Processor status register
Program counter
Note :
X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
(1
)
(
2
)
(
3
)
(
4
)
(
5
)
(
6
)
(
7
)
(
8
)
(
9
)
(
1
0
)
(
1
1
)
(
1
2
)
(
1
3
)
(
1
4
)
(
1
5
)
(
1
6
)
(
1
7
)
(
1
8
)
(
1
9
)
(
2
0
)
(
2
1
)
(
2
2
)
(
2
3
)
(
2
4
)
(
2
5
)
(
2
6
)
(
2
7
)
(
2
8
)
(
2
9
)
(
3
0
)
(
3
1
)
(
3
2
)
(
3
3
)
A
d
d
r
e
s
s Register contents
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
FF
16
01
16
00
16
00
16
FF
16
FF
16
FF
16
FF
16
00
16
P
o
r
t
P
0
(
P
0
)
P
o
r
t
P
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
0
D
)
P
o
r
t
P
1
(
P
1
)
P
o
r
t
P
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
1
D
)
P
o
r
t
P
2
(
P
2
)
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
2
D
)
P
o
r
t
P
3
(
P
3
)
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
3
D
)
P
o
r
t
P
4
(
P
4
)
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
4
D
)
P
o
r
t
P
0
,
P
1
,
P
2
p
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
U
L
L
0
1
2
)
P
o
r
t
P
3
p
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
U
L
L
3
)
P
o
r
t
P
4
p
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
U
L
L
4
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
S
I
O
2
C
O
N
1
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
S
I
O
2
C
O
N
2
)
S
e
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
(
S
I
O
2
)
T
r
a
n
s
m
i
t
/
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
T
B
/
R
B
)
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
I
O
S
T
S
)
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
C
O
N
)
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
A
R
T
C
O
N
)
B
a
u
d
r
a
t
e
g
e
n
e
r
a
t
o
r
(
B
R
G
)
P
W
M
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
W
M
C
O
N
)
P
W
M
p
r
e
s
c
a
l
e
r
(
P
R
E
P
W
M
)
P
W
M
r
e
g
i
s
t
e
r
(
P
W
M
)
P
r
e
s
c
a
l
e
r
1
2
(
P
R
E
1
2
)
T
i
m
e
r
1
(
T
1
)
T
i
m
e
r
2
(
T
2
)
T
i
m
e
r
X
Y
m
o
d
e
r
e
g
i
s
t
e
r
(
T
M
)
P
r
e
s
c
a
l
e
r
X
(
P
R
E
X
)
T
i
m
e
r
X
(
T
X
)
P
r
e
s
c
a
l
e
r
Y
(
P
R
E
Y
)
T
i
m
e
r
Y
(
T
Y
)
T
i
m
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
T
C
S
S
)
0 0 0 0 0 1 1 1
1 0 0 0 0 0 0 0
X X X X X X X X
0
0
0
0
1
6
0
0
0
1
1
6
0
0
0
2
1
6
0
0
0
3
1
6
0
0
0
4
1
6
0
0
0
5
1
6
0
0
0
6
1
6
0
0
0
7
1
6
0
0
0
8
1
6
0
0
0
9
1
6
0
0
1
2
1
6
0
0
1
3
1
6
0
0
1
4
1
6
0
0
1
5
1
6
0
0
1
6
1
6
0
0
1
7
1
6
0
0
1
8
1
6
0
0
1
9
1
6
0
0
1
A
1
6
0
0
1
B
1
6
0
0
1
C
1
6
0
0
1
D
1
6
0
0
1
E
1
6
0
0
1
F
1
6
0
0
2
0
1
6
0
0
2
1
1
6
0
0
2
2
1
6
0
0
2
3
1
6
0
0
2
4
1
6
0
0
2
5
1
6
0
0
2
6
1
6
0
0
2
7
1
6
0
0
2
8
1
6
1 1 1 0 0 0 0 0
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
R
e
g
i
s
t
e
r
c
o
n
t
e
n
t
s
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
(PS)
(PC
H
)
(PC
L
)
Address
X X X X X 1 X X
F
F
D
1
6
c
o
n
t
e
n
t
s
F
F
F
C
1
6
c
o
n
t
e
n
t
s
0 0 1 1 1 1 1 1
0 1 0 0 1 0 0 0
0 0 0 1 0 0 0 0
X X X X X X X X
X X
0 0 0 0 0 0
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