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參數(shù)資料
| 型號： | 3802 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | TRANS PREBIASED NPN 200MW SOT-23 |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 40/51頁 |
| 文件大?。?/td> | 692K |
| 代理商： | 3802 |
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MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
40
Note 1:
The RESET
OUT
output goes “H” in sync with the rise of the
φ
clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
Before
φ
ONW input set up time
After
φ
ONW input hold time
Before
φ
data bus set up time
After
φ
data bus hold time
Before RD ONW input set up time
Before WR ONW input set up time
After RD ONW input hold time
After WR ONW input hold time
Before RD data bus set up time
After RD data bus hold time
t
su(ONW–
φ
)
t
h(
φ
–ONW)
t
su(DB–
φ
)
t
h(
φ
–DB)
t
su
(ONW–RD)
t
su
(ONW–WR)
t
h(RD–ONW)
t
h(WR–ONW)
t
su(DB–RD)
t
h(RD–DB)
Symbol
Parameter
Limits
Typ.
Min.
–20
–20
60
ns
ns
ns
ns
ns
ns
ns
ns
Unit
0
–20
–20
65
0
Max.
φ
clock cycle time
φ
clock “H” pulse width
φ
clock “L” pulse width
After
φ
AD
15
–AD
8
delay time
After
φ
AD
15
–AD
8
valid time
After
φ
AD
7
–AD
0
delay time
After
φ
AD
7
–AD
0
valid time
SYNC delay time
SYNC valid time
RD and WR delay time
RD and WR valid time
After
φ
data bus delay time
After
φ
data bus valid time
RD pulse width, WR pulse width
RD pulse width, WR pulse width
(When one-wait is valid)
After AD
15
–AD
8
RD delay time
After AD
15
–AD
8
WR delay time
After AD
7
–AD
0
RD delay time
After AD
7
–AD
0
WR delay time
After RD AD
15
–AD
8
valid time
After WR AD
15
–AD
8
valid time
After RD AD
7
–AD
0
valid time
After WR AD
7
–AD
0
valid time
After WR data bus delay time
After WR data bus valid time
RESET
OUT
output delay time (Note 1)
RESET
OUT
output valid time (Note 1)
40
45
20
10
70
65
200
200
Symbol
Parameter
Limits
Typ.
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(X
IN
)
–10
t
c(X
IN
)
–10
6
6
3
15
t
c(X
IN
)
–10
3t
c(X
IN
)
–10
t
c(X
IN
)
–35
t
c(X
IN
)
–40
0
0
10
0
2t
c(X
IN
)
20
10
25
10
20
10
10
5
20
t
c(X
IN
)
–15
t
c(X
IN
)
–20
5
5
15
Max.
t
c(
φ
)
t
wH(
φ
)
t
wL(
φ
)
t
d(
φ
–AH)
t
v(
φ
–AH)
t
d(
φ
–AL)
t
v(
φ
–AL)
t
d(
φ
–SYNC)
t
v(
φ
–SYNC)
t
d(
φ
–WR)
t
v(
φ
–WR)
t
d(
φ
–DB)
t
v(
φ
–DB)
t
wL(RD)
t
wL(WR)
t
d(AH–RD)
t
d(AH–WR)
t
d(AL–RD)
t
d(AL–WR)
t
v(RD–AH)
t
v(WR–AH)
t
v(RD–AL)
t
v(WR–AL)
t
d(WR–DB)
t
v(WR–DB)
t
d
(RESET–RESET
OUT
)
t
v(
φ
–RESET)
Test conditions
Fig. 36
TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
SWITCHING CHARATERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
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