參數(shù)資料
型號(hào)： 3802
廠商： Mitsubishi Electric Corporation
英文描述： TRANS PREBIASED NPN 200MW SOT-23
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 39/51頁
文件大?。?/td> 692K
代理商： 3802
MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
39
Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output valid time (Note 2)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
140
200
30
30
30
40
30
30
Symbol
Parameter
Limits
Typ.
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
SWITCHING CHARACTERISTICS 1
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
t
c(S
CLK1
)/2–30
t
c(S
CLK2
)/2–160
t
c(S
CLK1
)/2–30
t
c(S
CLK2
)/2–160
–30
0
10
10
Max.
t
wH(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK1
)
t
wL(S
CLK2
)
t
d(S
CLK1
–T
X
D)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK1
–T
X
D)
t
v(S
CLK2
–S
OUT2
)
t
r(S
CLK1
)
t
f(S
CLK1
)
t
r(S
CLK2
)
t
f(S
CLK2
)
t
r(CMOS)
t
f(CMOS)
Test conditions
Fig. 36
Note1:
When the P4
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is “0”.
2:
When the P5
1
/S
OUT2
P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D
16
) is “0”.
3:
X
OUT
pin is excluded.
SWITCHING CHARACTERISTICS 2
(V
CC
= 3.0 to 5.5 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output valid time (Note 2)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
350
400
50
50
50
50
50
50
Symbol
Parameter
Limits
Typ.
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(S
CLK1
)/2–50
t
c(S
CLK2
)/2–240
t
c(S
CLK1
)/2–50
t
c(S
CLK2
)/2–240
–30
0
20
20
Max.
t
wH(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK1
)
t
wL(S
CLK2
)
t
d(S
CLK1
–T
X
D)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK1
–T
X
D)
t
v(S
CLK2
–S
OUT2
)
t
r(S
CLK1
)
t
f(S
CLK1
)
t
r(S
CLK2
)
t
f(S
CLK2
)
t
r(CMOS)
t
f(CMOS)
Test conditions
Fig. 36
Note1:
When the P4
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is “0”.
2:
When the P5
1
/S
OUT2
P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D
16
) is “0”.
3:
X
OUT
pin is excluded.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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