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參數(shù)資料
| 型號(hào)： | 37LV128-L |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | DIODE ZENER SINGLE 150mW 2.4Vz 5mA-Izt 0.083 50uA-Ir 1 SOD-523 3K/REEL |
| 中文描述： | 36K，64K的，和128K串行EPROM家庭 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 88K |
| 代理商： | 37LV128-L |
1996 Microchip Technology Inc.
DS21109E-page 3
37LV36/65/128
2.0
DATA
2.1
Data I/O
Three-state DATA output for reading and input during
programming.
3.0
CLK
3.1
Clock Input
Used to increment the internal address and bit
counters for reading and programming.
4.0
RESET/OE
4.1
Reset Input and Output Enable
A LOW level on both the CE and RESET/OE inputs
enables the data output driver. A HIGH level on
RESET/OE resets both the address and bit counters.
In the 37LVXXX, the logic polarity of this input is pro-
grammable as either RESET/OE or OE/RESET. This
document describes the pin as RESET/OE although
the opposite polarity is also possible. This option is
defined and set at device program time.
5.0
CE
5.1
Chip Enable Input
CE is used for device selection. A LOW level on both
CE and OE enables the data output driver. A HIGH
level on CE disables both the address and bit counters
and forces the device into a low power mode.
6.0
CEO
6.1
Chip Enable Output
This signal is asserted LOW on the clock cycle follow-
ing the last bit read from the memory. It will stay LOW
as long as CE and OE are both LOW. It will then follow
CE until OE goes HIGH. Thereafter, CEO will stay
HIGH until the entire EPROM is read again. This pin
also used to sense the status of RESET polarity when
Programming Mode is entered.
7.0
VPP
7.1
Programming Voltage Supply
Used to enter programming mode (+13 volts) and to
program the memory (+13 volts). Must be connected
directly to Vcc for normal Read operation. No over-
shoot above +14 volts is permitted.
8.0
CASCADING SERIAL EPROMS
Cascading Serial EPROMs provide additional memory
for multiple FPGAs configured as a daisy-chain, or for
future applications requiring larger configuration mem-
ories.
When the last bit from the first Serial EPROM is read,
the next clock signal to the Serial EPROM asserts its
CEO output LOW and disables its DATA line. The sec-
ond Serial EPROM recognizes the LOW level on its CE
input and enables its DATA output.
When configuration is complete, the address counters
of all cascaded Serial EPROMs are reset if RESET
goes LOW forcing the RESET/OE on each Serial
EPROM to go HIGH. If the address counters are not to
be reset upon completion, then the RESET/OE inputs
can be tied to ground.
Additional logic may be required if cascaded memories
are so large that the rippled chip enable is not fast
enough to activate successive Serial EPROMs.
9.0
STANDBY MODE
The 37LVXXX enters a low-power Standby Mode
whenever CE is HIGH. In Standby Mode, the Serial
EPROM consumes less than 100
output will remain in a high-impedance state regardless
of the state of the OE input.
10.0
PROGRAMMING MODE
μ
A of current. The
Programming Mode is entered by holding V
(+13 volts) for two clock edges and then holding V
V
DD
for one clock edge. Programming mode is exited
by driving a LOW on both CE and OE and then remov-
ing power from the device. Figures 4 through 7 show
the programming algorithm.
11.0
37LVXXX RESET POLARITY
PP
HIGH
PP
=
The 37LVXXX lets the user choose the reset polarity as
either RESET/OE or OE/RESET. Any third-party com-
mercial programmer should prompt the user for the
desired reset polarity.
The programming of the overflow word should be han-
dled transparently by the EPROM programmer; it is
mentioned here as supplemental information only.
The polarity is programmed into the first overflow word
location, maximum address+1. 00000000 in these
locations makes the reset active LOW, FFFFFFFF in
these locations makes the reset active HIGH. The
default condition is RESET active HIGH.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 37LV128-P | 36K, 64K, and 128K Serial EPROM Family |
| 37LV128-SN | 36K, 64K, and 128K Serial EPROM Family |
| 37LV128-TIL | DIODE ZENER SINGLE 500mW 2.7Vz 5mA-Izt 0.0741 20uA-Ir 1 SOD-123 3K/REEL |
| 37LV128-TIP | 36K, 64K, and 128K Serial EPROM Family |
| 3802 | TRANS PREBIASED NPN 200MW SOT-23 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 37LV128-P | 制造商:MICROCHIP 制造商全稱(chēng):Microchip Technology 功能描述:36K, 64K, and 128K Serial EPROM Family |
| 37LV128-SN | 制造商:MICROCHIP 制造商全稱(chēng):Microchip Technology 功能描述:36K, 64K, and 128K Serial EPROM Family |
| 37LV128T/L | 制造商:MICROCHIP 制造商全稱(chēng):Microchip Technology 功能描述:36K, 64K, and 128K Serial EPROM Family |
| 37LV128T/P | 制造商:MICROCHIP 制造商全稱(chēng):Microchip Technology 功能描述:36K, 64K, and 128K Serial EPROM Family |
| 37LV128T/SN | 制造商:MICROCHIP 制造商全稱(chēng):Microchip Technology 功能描述:36K, 64K, and 128K Serial EPROM Family |
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