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參數(shù)資料
| 型號(hào)： | 37C67X |
| 廠商： | SMSC Corporation |
| 英文描述： | ENHANCED SUPER I/O CONTROLLER WITH FAST IR |
| 中文描述： | 增強(qiáng)的超級(jí)I / O控制器，快速紅外線 |
| 文件頁(yè)數(shù)： | 6/194頁(yè) |
| 文件大小： | 546K |
| 代理商： | 37C67X |
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103
Table 43
Forward Channel Commands (HostAck Low)
Reverse Channel Commands (PeripAck Low)
D7
D[6:0]
0
Run-Length Count (0-127)
(mode 0011 0X00 only)
1
Channel Address (0-127)
Data Compression
The ECP port supports run length encoded
(RLE) decompression in hardware and can
transfer compressed data to a peripheral. Run
length encoded (RLE) compression in hardware
is not supported. To transfer compressed data
in ECP mode, the compression count is written
to the ecpAFifo and the data byte is written to
the ecpDFifo.
Compression
is
accomplished
by
counting
identical bytes and transmitting an RLE byte
that indicates how many times the next byte is
to
be
repeated.
Decompression
simply
intercepts
the
RLE
byte
and
repeats
the
following byte the specified number of times.
When a run-length count is received from a
peripheral,
the
subsequent
data
byte
is
replicated the specified number of times. A
run-length count of zero specifies that only one
byte of data is represented by the next data
byte, whereas a
run-length
count
of 127
indicates that the next byte should be expanded
to 128 bytes. To prevent data expansion,
however, run-length counts of zero should be
avoided.
Pin Definition
The drivers for nStrobe, nAutoFd, nInit and
nSelectIn are open-collector in mode 000 and
are push-pull in all other modes.
ISA Connections
The interface can never stall causing the host to
hang. The width of data transfers is strictly
controlled on an I/O address basis per this
specification. All FIFO-DMA transfers are byte
wide, byte aligned and end on a byte boundary.
(The PWord value can be obtained by reading
Configuration Register A,
cnfgA, described in
the next section.)
Single byte wide transfers
are
always possible with standard or PS/2
mode using program control of the control
signals.
Interrupts
The interrupts are enabled by serviceIntr in the
ecr register.
serviceIntr = 1 Disables the DMA and all of the
service interrupts.
serviceIntr = 0
Enables the selected interrupt
condition.
If the interrupting
condition is valid, then the
interrupt
is
generated
immediately when this bit is
changed from a 1 to a 0. This
can occur during Programmed
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