參數(shù)資料
型號(hào)： 3745SN
廠商： Linear Technology Corporation
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS
中文描述： 抗輻射高效，5安培開關(guān)穩(wěn)壓器
文件頁(yè)數(shù)： 21/32頁(yè)
文件大?。?/td> 309K
代理商： 3745SN
21
LT1374
1374fb
APPLICATIO
S I
FOR
ATIO
U
THERMAL CALCULATIONS
Power dissipation in the LT1374 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
W
U
U
P
R
V
V
ns I
V
f
SW
SW OUT
OUT
IN
OUT
IN
=
) (
)
+
(
)( )( )
2
24
Boost current loss:
P
V
I
V
BOOST
OUT
OUT
IN
=
(
)
2
50
/
Quiescent current loss:
P
V
V
V
V
Q
IN
OUT
OUT
IN
=
(
)
+
(
)
+
(
)
0 001
0 005
0 002
2
R
SW
= Switch resistance (
≈
0.07)
24ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with V
IN
= 10V, V
OUT
= 5V and I
OUT
= 3A:
P
W
P
W
P
W
SW
BOOST
Q
=
(
+
10
0 36
2
/
( )( )
=
+
=
=
( ) (
)
=
=
(
)
+
(
)
+
( ) (
)
=
0 07 3
.
5
24 10
3 10 500 10
0 32
.
068
.
5
3 50
10
0 15
.
10 0 001
5 0 005
.
5
0 002
.
10
0 04
.
2
9
3
2
.
.
Total power dissipation is 0.68 + 0.15 + 0.04 = 0.87W.
Thermal resistance for LT1374 package is influenced by
the presence of internal or backside planes. With a full
plane under the 16-lead TSSOP package, thermal resis-
tance will be about 40
°
C/W. To calculate die temperature,
use the proper thermal resistance number for the desired
package and add in worst-case ambient temperature:
T
J
= T
A
+
θ
JA
(P
TOT
)
With the TSSOP16 package (
θ
JA
= 40
°
C/W), at an ambient
temperature of 50
°
C,
T
J
= 50 + 40 (0.87) = 85
°
C
For the DD package with a good copper plane under the
device, thermal resistance will be about 30
°
C/W. For the
conditions above:
T
J
= 50 + 30 (0.87) = 76
°
C
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
FREQUENCY COMPENSATION
Loop frequency compensation of switching regulators
can be a rather complicated problem because the reactive
components used to achieve high efficiency also intro-
duce multiple poles into the feedback loop. The inductor
and output capacitor on a conventional step-down con-
verter actually form a resonant tank circuit that can exhibit
peaking and a rapid 180
°
phase shift at the resonant
frequency. By contrast, the LT1374 uses a “current mode”
architecture to help alleviate phase shift created by the
inductor. The basic connections are shown in Figure 9.
Figure 10 shows a Bode plot of the phase and gain of the
power section of the LT1374, measured from the V
C
pin to
the output. Gain is set by the 5.3A/V transconductance of
the LT1374 power section and the effective complex
impedance from output to ground. Gain rolls off smoothly
above the 600Hz pole frequency set by the 100
μ
F output
capacitor. Phase drop is limited to about 70
°
. Phase
recovers and gain levels off at the zero frequency (
≈
16kHz)
set by capacitor ESR (0.1
).
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