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參數(shù)資料
| 型號： | 3710EFE |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Secondary Side Synchronous Post Regulator |
| 中文描述： | 二次側同步后穩(wěn)壓器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 226K |
| 代理商： | 3710EFE |
LT3710
7
3710f
APPLICATIU
W
U
U
TRANSFORMER
SECONDARY VOLTAGE
SYNC SIGNAL V
RESET
RAMP V
CSET
VA
OUT
SWITCH NODE V
SW
3710 F02
TGATE
BGATE
I
L
D
1
T
V
SP
V
S
V
RESET
T
D
2
T
V
SP
T
Figure 2. Leading Edge Modulation,
Trailing Edge Synchronization
OPERATIOU
To generate isolated multiple outputs, most systems use
either multiple secondary windings or cascade regulators
for each additional output. Multiple secondary windings
sacrifice regulation of the auxiliary outputs. Cascaded
regulators require a larger inductor for the main output,
because all of the power is processed in series.
By generating the auxiliary output(s) from the secondary
winding of the main output, the LT3710 allows for parallel
processing of the output power. This minimizes the main
output inductor size and directly regulates the auxiliary
output. With synchronous rectification, the system effi-
ciency is greatly improved.
Refering to the Block Diagram, the LT3710 basic functions
include a voltage amplifier, VA, to regulate the output
voltage to within typically 1.5%, a voltage mode PWM with
trailing edge synchronization and leading edge modula-
tion, a current limit amplifier, CA1, and high speed syn-
chronous switch drivers.
During normal operation (see Figure 2), a switching cycle
begins at the falling edge of the transformer secondary
voltage V
S
. The internal oscillator is reset, turning off the
top MOSFET M1 and turning on the bottom MOSFET M2.
During this portion of the cycle, the inductor current is
discharged by the output voltage V
OUT2
. The transformer
secondary voltage V
S
will go high during this portion of the
cycle. Since M1 is off, the switch node voltage V
SW
remains zero. The inductor current continues to be dis-
charged by the output voltage V
OUT2
. This condition lasts
Synchronization and Oscillation Frequency Setting
The switching is synchronized to the secondary winding
falling edge and the synchronization threshold is typically
2.5V. The synchronization falling edge triggers an internal
inverted ramp (see Figure 2) and starts a new switching
cycle for the leading edge voltage mode PWM. The reason
for using leading edge modulation is to keep the trans-
former primary side peak current sensing undisturbed.
For proper synchronization, the oscillator frequency should
be set lower than the system switching frequency with
tolerances taken into account.
f
OSC
< (f
SL
0.8)
f
SL
is the low limit of the system switching frequency and
0.8 is the tolerance of f
OSC
.
For example, a system of 200KHz with 15% tolerance,
then f
SL
= 200k 85% = 170kHz; and f
OSC
< (170k 0.8),
f
OSC
should be set below 136kHz.
Once f
OSC
is determined, CSET can be calculated by
CSET = (107250pf/f
OSC(kHz)
) – 50pF.
For f
OSC
= 100kHz, CSET = 1022.5pF.
until the ramp signal intersects the feedback error ampli-
fier output VA
OUT
. The top MOSFET M1 turns on, pulling
the switch node voltage to V
S
. The inductor current of the
LT3710 circuit is then charged by V
S
– V
OUT2
. The effective
on time of this buck circuit ends when the secondary
voltage becomes zero. The next cycle repeats.
The ideal equation for duty cycle of the LT3710 is:
D2 = V
OUT2
/V
SP
where V
OUT2
is the auxiliary output voltage, V
SP
is the
amplitude of the secondary voltage and D2 is the duty
cycle of the switching node voltage V
SW
, as defined in
Figure 2.
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