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參數(shù)資料
| 型號(hào)： | 33C408RTFS-20 |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | SRAM |
| 英文描述： | 4 Megabit (512K x 8-Bit) CMOS SRAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 20 ns, DFP32 |
| 封裝： | DFP-32 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 241K |
| 代理商： | 33C408RTFS-20 |
9
All data sheets are subject to change without notice
2002 Maxwell Technologies
All rights reserved.
4 Megabit (512K x 8-Bit) CMOS SRAM
33C408
04.16.02 REV 8
W
RITE
C
YCLE
N
OTE
:
1.
All write cycle timing is referenced from the last valid address to the first transition address.
2.
A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition
among CS going low and WE going low: A write ends at the earliest transition among CS going high
and WE going high. t
WP
is measured from beginning of write to the end of write.
3.
t
CW
is measured from the later of CS going low to end of write.
4.
t
AS
is measured from the address valid to the beginning of write.
5.
t
WR
is measured form the end of write to the address change. TWR applied in case a write ends as CS,
or WR going high.
6.
If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
7.
For common I/O applications, minimization or elimination of bus contention conditions is necessary
during read and write cycle.
8.
IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high
impedance state.
9.
D
OUT
is the read data of the new address.
10.
When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading
to the output should not be applied.
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| 33C408RTFS-25 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:4 Megabit (512K x 8-Bit) CMOS SRAM |
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