- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358627 > 33991 (Motorola, Inc.) Gauge Driver Integrated Circuit PDF資料下載
參數(shù)資料
| 型號： | 33991 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Gauge Driver Integrated Circuit |
| 中文描述： | 儀表驅(qū)動集成電路 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 660K |
| 代理商： | 33991 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33991
9
Characteristic
Symbol
Min
Typ
Max
Unit
SPI Timing Interface
Recommended Frequency of SPI Operation
f
SPI
—
1
3
MHz
Falling edge of CS to Rising Edge of SCLK Required Setup Time) (Note9)
T
LEAD
—
50
167
ns
Falling edge of SCLK to Rising Edge of CS (Required Setup Time)(Note9)
T
LAG
—
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time) (Note9)
TS
LSU
—
25
83
ns
Falling Edge of SCLK to SI (Required Hold Time) (Note9)
TSI
(HOLD)
—
25
83
ns
SO Rise Time (CL = 200 pF)
Tr
SO
—
25
50
ns
SO Fall Time (CL = 200 pF)
Tf
SO
—
25
50
ns
SI, CS, SCLK, Incoming Signal Rise Time (Note10)
Tr
SI
—
—
50
ns
SI, CS, SCLK, Incoming Signal Fall Time (Note10)
Tf
SI
—
—
50
ns
Falling Edge of RST to Rising Edge of RST (Required Setup Time) (Note9)
Tw
RST
—
—
3
μs
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note9)
(Note11)
T
CS
—
—
5
μs
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note9)
T
EN
—
—
5
μs
Time from Falling Edge of CS to SO Low Impedance (Note12)
T
SO(EN)
—
—
145
ns
Time from Rising Edge of CS to SO High Impedance (Note13)
T
SO(DIS)
—
1.3
4
μs
Time from Rising Edge of SCLK to SO Data Valid (Note14) 0.2 V
DD
< = SO
> = 0.8 V
DD
, CL = 200 pF
T
VALID
—
65
105
ns
Notes:
9.
10.
11.
12.
13.
14.
The maximum setup times specified for the 33991 is the minimum time needed from the microcontroller to guarantee correct operation.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
This value is for a 1 MHz calibrated internal clock; it will change proportionally as the internal clock frequency changes.
Time required for output status data to be available for use at SO. 1 K
load on SO.
Time required for output status data to be terminated at SO. 1 K
load on SO.
Time required to obtain valid data out from SO following the rise of SCLK.
T
he device shall meet all SPI interface-timing requirements specified in the
SPI Interface Timing
, over the temperature range specified in the
environmental requirements section. Digital Interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The
device shall be fully functional for slower clock speeds.
STATIC ELECTRICAL CHARACTERISTICS
(Characteristics noted under conditions 4.75 V < V
DD
< 5.25 V, -40° C < TJ < 150° C, unless otherwise noted)
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
相關PDF資料 |
PDF描述 |
|---|---|
| 33BS | surface mount silicon Zener diodes |
| 33C408 | 4 Megabit (512K x 8-Bit) CMOS SRAM |
| 33C408RPFB-20 | 4 Megabit (512K x 8-Bit) CMOS SRAM |
| 33C408RPFB-25 | 4 Megabit (512K x 8-Bit) CMOS SRAM |
| 33C408RPFB-30 | 4 Megabit (512K x 8-Bit) CMOS SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 33-991 | 制造商:Ideal Industries Inc 功能描述:LTKII,350MHZ,CAT6 W/CAT6 ADPT |
| 3399-1 | 制造商:3M 功能描述:3399-1 |
| 33992 | 制造商:Ideal Industries Inc 功能描述:LTKII500MHZ,CAT6A W/CAT6A ADPT |
| 33992510000001 | 功能描述:電纜組件 CABLE KIT RoHS:否 制造商:Molex 產(chǎn)品:Power Assemblies 類型:Cable Assembly 連接器端口 A:No Connector 連接器端口 A 管腳計數(shù):4 連接器端口 B:No Connector 連接器端口 B 管腳計數(shù): 型式:Male 線規(guī) - 美國線規(guī)（AWG）:20, 28 長度:0.305 m 顏色:Black, Red |
| 33993 | 制造商:Ideal Industries Inc 功能描述:LTKII1000MHZ,CAT7A W/CAT6AADPT |
發(fā)布緊急采購，3分鐘左右您將得到回復。