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參數(shù)資料
| 型號： | 3341-56 |
| 廠商： | Peregrine Semiconductor |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL INTEGER-N 3GHZ 20QFN |
| 標準包裝： | 6,000 |
| 系列： | UltraCMOS™ |
| 類型： | 時鐘緩沖器/驅(qū)動器，多路復用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，RF 儀表系統(tǒng)，無線基站 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3GHz |
| 電源電壓： | 2.85 V ~ 3.15 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 20-QFN（4x4） |
| 包裝： | 帶卷 (TR) |
Page 1 of 17
Document No. 70-0053-05
│ www.psemi.com
2005-8 Peregrine Semiconductor Corp. All rights reserved.
The PE3341 is a high performance integer-N PLL with
embedded EEPROM capable of frequency synthesis up to
2700 MHz with a speed-grade option to 3000 MHz. The
EEPROM allows designers to permanently store control bits,
allowing easy configuration of self-starting synthesizers. The
superior phase noise performance of the PE3341 is ideal for
applications such as sonet, wireless base stations, fixed
wireless, and RF instrumentation systems.
The PE3341 features a ÷10/11 dual modulus prescaler,
counters, a phase comparator, and a charge pump as shown in
Figure 1. Counter values are programmable through a three-
wire serial interface.
The PE3341 UltraCMOS Phase Locked-Loop is
manufactured in Peregrine’s patented Ultra Thin Silicon
(UTSi) CMOS process, offering excellent RF performance
with the economy and integration of conventional CMOS.
Product Specification
2700 MHz Integer-N PLL
with Field-Programmable EEPROM
Product Description
Figure 1. Block Diagram
PE3341
Features
Field-programmable EEPROM for self-
starting applications
Standard 2700 MHz operation,
3000 MHz speed-grade option
÷10/11 dual modulus prescaler
Internal charge pump
Serial programmable
Low power — 20 mA at 3 V
Ultra-low phase noise
Available in 20-lead 4x4 mm QFN
package
Enhancement
Register
(8-bit)
F
in
F
in
Prescaler
÷10/11
M Counter
÷2 to ÷512
20
Serial
Interface
Mux
R Counter
÷1 to ÷64
f
r
Phase
Detector
6
S_WR
PD_U
PD_D
V
PP
EELoad
EESel
FSel
Clock
Data
20
LD
Cext
CP
Primary
Register
(20-bit)
EE
Register
(20-bit)
Transfer
Logic
EEPROM
ENH
E_WR
Charge
Pump
13
6
Secondary
Register
(20-bit)
2k
Obsolete
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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