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參數(shù)資料
| 型號： | 3336-52 |
| 廠商： | Peregrine Semiconductor |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL INTEGER-N 3GHZ 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | UltraCMOS™ |
| 類型： | 預(yù)分頻器，整數(shù) N |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.85 V ~ 3.15 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 1046-1014-6 |
Product Specification
PE3336
Document No. 70-0033-05
│ www.psemi.com
Page 7 of 13
2005-2011 Peregrine Semiconductor Corp. All rights reserved.
Functional Description
The PE3336 consists of a prescaler, counters, a
phase detector and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via serial bus,
parallel bus, or hardwired direct to the pins. There
are also various operational and test modes and
lock detect.
Figure 3. Functional Block Diagram
Control
Logic
R Counter
(6-bit)
Phase
Detector
fc
PD_U
PD_D
R(5:0)
M(8:0)
A(3:0)
D(7:0)
Sdata
Control
Pins
fr
Modulus
Select
10/11
Prescaler
M Counter
(9-bit)
2k
Cext
fp
Fin
Obsolete
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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