參數(shù)資料
型號(hào): 3256A
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable High Density PLD
中文描述: 在系統(tǒng)可編程高密度可編程邏輯器件
文件頁數(shù): 7/13頁
文件大小: 163K
代理商: 3256A
Specifications
ispLSI 3256A
7
UA E
Internal Timing Parameters
1
Over Recommended Operating Conditions
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036C/3256A
Inputs
UNITS
-70
MIN.
-50
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
24 I/O Register Bypass
25 I/O Latch Delay
26 I/O Register Setup Time before Clock
27 I/O Register Hold Time after Clock
3.3
15.8
ns
ns
ns
ns
8.6
-7.0
GRP
t
grp
GLB
t
4ptbp
t
4ptbp
28 I/O Register Clock to Out Delay
29 I/O Register Reset to Out Delay
5.3
4.9
ns
ns
30 GRP Delay
4.1
ns
31 4 Product Term Bypass Path Delay (Comb.)
32 4 Product Term Bypass Path Delay (Reg.)
7.6
7.6
ns
ns
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
ORP
t
orp
t
orpbp
33 1 Product Term/XOR Path Delay
34 20 Product Term/XOR Path Delay
35 XOR Adjacent Path Delay
36 GLB Register Bypass Delay
8.8
10.1
11.1
0.1
ns
ns
ns
ns
37 GLB Register Setup Time before Clock
38 GLB Register Hold Time after Clock
2.4
8.2
ns
ns
39 GLB Register Clock to Output Delay
2.2
ns
3
40 GLB Register Reset to Output Delay
41 GLB Product Term Reset to Register Delay
42 GLB Product Term Output Enable to I/O Cell Delay
43 GLB Product Term Clock Delay
3.8
14.2
7.3
8.5
ns
ns
ns
ns
4.3
44 ORP Delay
45 ORP Bypass Delay
3.6
1.6
ns
ns
6.2
-5.2
1.8
6.0
2.4
12.4
4.2
3.6
3.0
5.9
5.9
6.4
7.4
8.1
0.1
1.8
2.8
10.5
5.4
6.3
3.2
2.7
1.2
-90
MIN. MAX.
5.7
-3.7
1.0
4.8
1.9
10.9
4.2
2.8
2.4
4.8
4.8
5.4
6.4
6.9
0.1
1.6
2.6
8.6
4.9
5.3
2.8
2.3
0.9
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