參數(shù)資料
型號: 29F040C-90
廠商: Macronix International Co., Ltd.
英文描述: 4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 5V ONLY EQUAL SECTOR FLASH MEMORY
中文描述: 4分位[為512k × 8] CMOS單電壓5V只等于部門閃存
文件頁數(shù): 10/38頁
文件大?。?/td> 592K
代理商: 29F040C-90
10
P/N:PM1201
REV. 1.0, DEC. 20, 2005
MX29F040C
the rising edge of the final WE# or CE#, whichever hap-
pens first pulse in the command sequence.
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CE# to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 4 to compare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on Q7-Q0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase opera-
tion. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta-
tus as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this
case, the system must start at the beginning of the al-
gorithm when it returns to determine the status of the
operation.
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE# or CE#, whichever
happens first pulse in the command sequence (prior to
the program or erase operation), and during the sector
time-out.
During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE# or CE# to
control the read cycles. When the operation is complete,
Q6 stops toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Auto-
matic Erase algorithm is in progress), Q6 toggling. When
the device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to de-
termine which sectors are erasing or erase-suspended.
Alternatively, the system can use Q7.
If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program command
sequence is written, then returns to reading array data.
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algorithm
is complete.
Table 4 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit I is valid after
相關PDF資料
PDF描述
29F080-12 8M-BIT [1024K x 8] CMOS EQUAL SECTOR FLASH MEMORY
29F080-70 8M-BIT [1024K x 8] CMOS EQUAL SECTOR FLASH MEMORY
29F080-90 8M-BIT [1024K x 8] CMOS EQUAL SECTOR FLASH MEMORY
29F1610 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
29F1610A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
相關代理商/技術參數(shù)
參數(shù)描述
29F0418-0SR (900PC RL) 制造商:Laird Technologies Inc 功能描述:SMD,6.1X4.5MM,6A I MAX,83 OHM,GULL WING,4 LINES,-55-+125,BLK - Tape and Reel
29F0418-0SR-10 功能描述:信號調節(jié) 83ohms 100MHz 6A Thru-hole RoHS:否 制造商:EPCOS 產品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel
29F0418-1SR 功能描述:FERRITE 6A 119 OHM SMD RoHS:否 類別:濾波器 >> 鐵氧體磁珠和芯片 系列:- 標準包裝:1,000 系列:EMI1812 頻率對應阻抗:120 歐姆 @ 100MHz 額定電流:200mA DC 電阻(DCR):最大 400 毫歐 濾波器類型:差模 - 單線 封裝/外殼:1812(4532 公制) 安裝類型:表面貼裝 包裝:帶卷 (TR) 高度(最大):0.069"(1.75mm) 尺寸/尺寸:0.177" L x 0.126" W(4.50mm x 3.20mm) 其它名稱:Q1712807A
29F0418-1SR (900PC RL) 制造商:Laird Technologies Inc 功能描述:SMD,6.1X4.5MM,6A I MAX,119 OHM,GULL WING,4 LINES,-55-+125 - Tape and Reel
29F0418-1SR-10 功能描述:EMI/RFI 抑制器及鐵氧體 119ohms 100MHz 6A Thru-hole RoHS:否 制造商:Fair-Rite 產品:Ferrite Cores 阻抗:365 Ohms 容差: 最大直流電流: 最大直流電阻: 工作溫度范圍:- 55 C to + 125 C 封裝 / 箱體: 端接類型:SMD/SMT