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參數(shù)資料
| 型號： | 28F400B3 |
| 廠商： | Intel Corp. |
| 英文描述： | SMART 3 ADVANCED BOOT BLOCK WORD-WIDE |
| 中文描述： | 智能3高級啟動塊字寬 |
| 文件頁數(shù)： | 16/49頁 |
| 文件大?。?/td> | 427K |
| 代理商： | 28F400B3 |
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SMART 3 ADVANCED BOOT BLOCK
–WORD-WIDE
E
16
PRELIMINARY
(erase suspend to program, erase suspend to read
and program suspend to read) are available only
during suspended operations. These modes are
reached using the commands summarized in
Table 4. A comprehensive chart showing the state
transitions is in Appendix B.
3.2.1
READ ARRAY
When RP# transitions from V
IL
(reset) to V
IH
, the
device will be in the read array mode and will
respond to the read control inputs (CE#, address
inputs, and OE#) without any commands being
written to the CUI.
When the device is in the read array mode, four
control signals must be controlled to obtain data at
the outputs.
WE# must be logic high (V
IH
)
CE# must be logic low (V
IL
)
OE# must be logic low (V
IL
)
RP# must be logic high (V
IH
)
In addition, the address of the desired location must
be applied to the address pins.
If the device is not in read array mode, as would be
the case after a program or erase operation, the
Read Array command (FFH) must be written to the
CUI before array reads can take place.
Table 4. Command Codes and Descriptions
Code
Device Mode
Description
00
Invalid/
Reserved
Unassigned commands that should not be used. Intel reserves the right to
redefine these codes for future functions.
FF
Read Array
Places the device in read array mode, such that array data will be output on the
data pins.
40
Program
Set-Up
This is a two-cycle command. The first cycle prepares the CUI for a program
operation. The second cycle latches addresses and data information and
initiates the WSM to execute the Program algorithm. The flash outputs status
register data when CE# or OE# is toggled. A Read Array command is required
after programming to read array data. See Section 3.2.4.
10
Alternate
Program Set-Up
(See 40H/Program Set-Up)
20
Erase
Set-Up
Prepares the CUI for the Erase Confirm command. If the next command is not
an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the
status register to a
“1,” (b) place the device into the read status register mode,
and (c) wait for another command. See Section 3.2.5.
D0
Program
Resume
Erase Resume/
Erase Confirm
If the previous command was an Erase Set-Up command, then the CUI will
close the address and data latches, and begin erasing the block indicated on the
address pins. If a program or erase operation was previously suspended, this
command will resume that operation.
During program/erase, the device will respond only to the Read Status Register,
Program Suspend/Erase Suspend commands and will output status register
data when CE# or OE# is toggled.
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