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參數(shù)資料
| 型號： | 28F320S3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 V、32MB FlashFile Memory(3 V、32M位FlashFile 存儲器) |
| 中文描述： | 3伏，32MB的FlashFile內(nèi)存（3伏，32位FlashFile存儲器） |
| 文件頁數(shù)： | 29/53頁 |
| 文件大小： | 331K |
| 代理商： | 28F320S3 |
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E
28F160S3/28F320S3
29
PRELIMINARY
Table 13. Write Protection Alternatives
Operation
Block
Lock-
Bit
WP#
Effect
Program and
0
V
IL
or V
IH
Block erase and programming enabled
Block Erase
1
V
IL
Block is locked. Block erase and programming disabled
V
IH
Block lock-bit override. Block erase and programming enabled
Full Chip Erase
0,1
V
IL
All unlocked blocks are erased
X
V
IH
Block lock-cit override. All blocks are erased
Set or Clear
X
V
IL
Set or clear block lock-bit disabled
Block Lock-Bit
V
IH
Set or clear block lock-bit
enabled
Table 14. Configuration Coding Definitions
Reserved
Pulse on
Write
Complete
Pulse on
Erase
Complete
bits 7
–2
bit 1
bit 0
DQ
7
–DQ
2
= Reserved
DQ
1
/DQ
0
= STS Pin Configuration Codes
00 =
default, level mode RY/BY#
(device ready) indication
01 =
pulse on Erase complete
10 =
pulse on Flash Program complete
11 = pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse
mode such that the STS pin pulses low then high
when the operation indicated by the given
configuration is completed.
Configuration Command Sequences for STS pin
configuration (masking bits D
7
–
D
2
to 00h) are as
follows:
Default RY/BY# level mode
ER INT (Erase Interrupt):
Pulse-on-Erase Complete
PR INT (Program Interrupt):
Pulse-on-Flash-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
B8h, 00h
B8h, 01h
B8h, 02h
DQ
7
–
DQ
2
are reserved for future use.
default (DQ
1
/DQ
0
= 00) RY/BY#, level mode
—used to control HOLD to a memory controller to
prevent accessing a flash memory subsystem while
any flash device's WSM is busy.
configuration 01
—used to generate a system interrupt pulse when
any flash device in an array has completed a block
erase or sequence of queued block erases. Helpful
for reformatting blocks after file system free space
reclamation or ‘cleanup’
ER INT, pulse mode
(1)
configuration 10
—used to generate a system interrupt pulse when
any flash device in an array has complete a
program operation. Provides highest performance
for servicing continuous buffer write operations.
PR INT, pulse mode
(1)
configuration
—used to generate system interrupts to trigger
servicing of flash arrays when either erase or flash
program operations are completed when a common
interrupt service routine is desired.
ER/PR INT, pulse mode
(1)
NOTE:
1.
When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
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相關(guān)代理商/技術(shù)參數(shù) |
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| 28F400B5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMART 5 BOOT BLOCK. FLASH MEMORY FAMILY 2. 4. 8 MBIT |
| 28F400B5WG8BET | 制造商: 功能描述: 制造商:Micron Technology Inc 功能描述: 制造商:undefined 功能描述: |
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