參數(shù)資料
型號(hào)： 28F320S3
廠商： Intel Corp.
英文描述： 3 V、32MB FlashFile Memory(3 V、32M位FlashFile 存儲(chǔ)器)
中文描述： 3伏，32MB的FlashFile內(nèi)存（3伏，32位FlashFile存儲(chǔ)器）
文件頁數(shù)： 26/53頁
文件大?。?/td> 331K
代理商： 28F320S3
28F160S3/28F320S3
E
26
PRELIMINARY
This two-step command sequence of setup followed
by execution ensures that block contents are not
accidentally erased. An invalid Full Chip Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to 1. Also,
reliable full chip erasure can only occur when
V
CC
= V
CC1/2
and V
PP
= V
PPH1/2/3
.
In the absence of
these voltages, block contents are protected
against erasure.
If full chip erase is attempted while
V
PP
≤
V
PPLK
, SR.3 and SR.5 will be set to 1.
When
WP# = V
IL
, only unlocked blocks are erased.
Full
chip erase cannot be suspended.
4.8
Write to Buffer Command
To program the flash device via the write buffers, a
Write to Buffer command sequence is initiated. A
variable number of bytes or words, up to the buffer
size, can be written into the buffer and programmed
to the flash device. First, the Write to Buffer Setup
command is issued along with the Block Address.
At this point, the XSR information is loaded and
XSR.7 indicates that another Write to Buffer
command is possible. If XSR.7 = 0, no write buffer
is available. To retry, continue monitoring XSR.7 by
issuing the Write to Buffer Setup command with the
Block Address until XSR.7 = 1. When XSR.7
transitions to a
“1,” the buffer is ready for loading.
Next, a word or byte count is issued at a valid
address within the block. On the next write, a
device start address is given along with the write
buffer
data.
For
maximum
performance and lower power, align the start
address at the beginning of a write buffer boundary.
Subsequent writes must supply additional device
addresses and data, depending on the count. All
subsequent addresses must lie within the start
address plus the count.
programming
After the final buffer data is given, a Write Confirm
command is issued. This initiates the WSM to begin
copying the buffer data to the flash memory. If a
command other than Write Confirm is written to the
device, an “Invalid Command/Sequence” error will
be generated and status register bits SR.5 and
SR.4 will be set to “1.” For additional buffer writes,
issue another Write to Buffer Setup command and
check XSR.7. The write buffers can be loaded while
the WSM is busy as long as XSR.7 indicates that a
buffer is available. Refer to Figure 6 for the
Write to
Buffer Flowchart
.
If an error occurs while writing, the device will stop
programming, and status register bit SR.4 will be
set to a “1” to indicate a program failure. Any time a
media failure occurs during a program or an erase
(SR.4 or SR.5 is set), the device will not accept any
more Write to Buffer commands. Additionally, if the
user attempts to write past an erase block boundary
with a Write to Buffer command, the device will
abort programming. This will generate an “Invalid
Command/Sequence” error and status register bits
SR.5 and SR.4 will be set to “1.” To clear SR.4
and/or SR.5, issue a Clear Status Register
command.
Reliable buffered programming can only occur
when V
CC
= V
CC1/2
and V
= V
PPH1/2/3
. If
programming is attempted while V
,
status register bits SR.4 and SR.5 will be set to “1.”
Programming attempts with invalid V
and V
voltages produce spurious results and should not
be attempted. Finally, successful programming
requires that the corresponding Block Lock-Bit be
cleared, or WP# = V
IH
. If a buffered write is
attempted when the corresponding Block Lock-Bit
is set and WP# = V
IL
, SR.1 and SR.4 will be set to
“1.”
4.9
Byte/Word Program Commands
Byte/Word programming is executed by a two-cycle
command sequence. Byte/Word Program setup
(standard 40H or alternate 10H) is written, followed
by a second write that specifies the address and
data (latched on the rising edge of WE#). The WSM
then takes over, controlling the program and verify
algorithms internally. After the write sequence is
written, the device automatically outputs status
register data when read. The CPU can detect the
completion of the program event by analyzing STS
in level RY/BY# mode or status register bit SR.7.
When programming is complete, status register bit
SR.4 should be checked. If a programming error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for “1”s that
do not successfully program to “0”s. The CUI
remains in read status register mode until it
receives another command. Refer to Figure 7 for
the
Single Word/Byte Program Flowchart
.
Also, Reliable byte/word programming can only
occur when V
CC
= V
CC1/2
and V
PP
= V
PPH1/2/3
.
In the
absence of this high voltage, contents are protected
against programming.
If a byte/word program is
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