參數(shù)資料
型號： 25C256
廠商： Microchip Technology Inc.
英文描述： 256K 5.0V SPI Bus Serial EEPROM(4.5~5.5V,256K位,SPI總線串行EEPROM)
中文描述： 256K 5.0V SPI總線串行EEPROM（4.5?5.5V的，256K位和SPI總線串行EEPROM的）
文件頁數(shù)： 104/170頁
文件大小： 4191K
代理商： 25C256
PIC16F62X
DS40300C-page 102
Preliminary
2003 Microchip Technology Inc.
14.6.1
RB0/INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or
falling, if INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the interrupt service
routine before re-enabling this interrupt. The RB0/INT
interrupt can wake-up the processor from SLEEP, if the
INTE bit was set prior to going into SLEEP. The status
of the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 14.9 for details on SLEEP, and Figure 14-17
for timing of wake-up from SLEEP through RB0/INT
interrupt.
14.6.2
TMR0 INTERRUPT
An overflow (FFh
→
00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be
enabled/disabled
by
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
setting/clearing
T0IE
14.6.3
PORTB INTERRUPT
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the RBIE (INTCON<4>)
bit. For operation of PORTB (Section 5.2).
14.6.4
COMPARATOR INTERRUPT
See Section 9.6 for complete description of comparator
interrupts.
FIGURE 14-15:
INT PIN INTERRUPT TIMING
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC
PC+1
PC+1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC+1)
Inst (PC-1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
Note
1:
2:
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
CLKOUT is available in ER and INTRC Oscillator mode.
For minimum width of INT pulse, refer to AC specs.
INTF is enabled to be set anytime during the Q4-Q1 cycles.
3:
4:
5:
(1)
(1)
(4)
(5)
(2)
(3)
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