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| 型號： | 25260C |
| 英文描述： | AMD MirrorBit? White Paper |
| 中文描述： | AMD公司的MirrorBit？白皮書 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 147K |
| 代理商： | 25260C |
AMD MirrorBit
2
Distinctive Features
Two bits of data stored in one
memory cell.
– This reduces costs
and enables low-cost, high-density Flash
memory.
Simple and symmetric cell architecture.
– This makes the device easy to
manufacture.
Two distinct charge storage areas with-
in one cell.
– This increases reliability and
data integrity.
Each unit of charge individually
programmed and erased.
– Allows high performance and high
reliability.
Full charge stored at each end of the
cell.
– Enables higher levels of reliability
and performance.
Products designed to be completely
pin-compatible with AMD’s current
64Mb LV Flash.
– Provides a seamless
migration path from AMD's single bit
Flash devices.
BENEFITS
The AMD MirrorBit architecture breaks the
traditional trade-off between cost and
performance. For the first time in history,
Flash memory designers and users can expect
high levels of performance and reliability as
well as the industry’s leading cost structure.
Customers therefore are no longer forced to
sacrifice reliability or performance for the sake
of cost.
AMD’s MirrorBit based products have the
same performance, endurance and reliability as
AMD’s standard 3 Volt products. Products
based on this new architecture are completely
pin-compatible with AMD’s standard 3 Volt
(LV product family) and offer a simple
migration path for customers from the current
LV family of products to higher densities such
as 256 Mb and eventually 1Gb. Since these
products are offered in
the same packages
and with the same pinouts
as AMD’s current
LV family of products, AMD’s customers can
easily migrate their existing designs to
MirrorBit based Flash.
Most importantly, MirrorBit Flash devices
are
available today
, so designers can
immediately enjoy MirrorBit technology's
many benefits.
In addition to offering low cost and high
reliability, products based on the MirrorBit
architecture also offer two new performance-
enhancing features, a read and write page
buffer that increases data throughput. As
device densities increase data input and output
become a major bottleneck and this limits
how fast data gets in and out of the device.
Since the MirrorBit architecture is well suited
for ultra-high density Flash memory devices,
products based on MirrorBit architecture offer
these page buffers to further improve
functionality and device performance.
MirrorBit Cell Diagram
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