參數(shù)資料
型號: 25260C
英文描述: AMD MirrorBit? White Paper
中文描述: AMD公司的MirrorBit?白皮書
文件頁數(shù): 3/10頁
文件大?。?/td> 147K
代理商: 25260C
AMD MirrorBit
White Paper
OVERVIEW
AMD continues to revolutionize the world of Flash memory. In 1991 AMD introduced negative gate
erase, a revolutionary architecture that enabled highly reliable, single power Flash memory. In 2001,
AMD announced the MirrorBit architecture, which – for the first time – enables a Flash memory
product to
hold twice as much data as standard Flash,
without compromising device
endurance, performance or reliability
. This new architecture offers customers a highly reliable
and low-cost, Flash memory solution.
The MirrorBit cell doubles the storage capability of the basic Flash memory cell and therefore
enables low-cost, high-density Flash memory products. Unlike competing multi-level cell (MLC)
technology, the MirrorBit architecture delivers this enhanced storage without compromising device
performance or reliability. This revolutionary architecture is the result of years of research and
development on the design, processing, testing and characterization of multi-bit cells that have
culminated in AMD’s patented MirrorBit architecture.
The MirrorBit architecture’s ability to store two bits of data in one cell, without compromising data
integrity, is achieved by storing each of the two units of charge individually, and in a different
location, within a single memory cell. Since each bit in the MirrorBit memory cell is in a physically
different location, the bits are independent and this allows AMD to offer the same performance
and reliability as standard single-bit Flash memory products.
Customers can benefit from this revolutionary architecture in several ways:
Low-cost Flash memory devices
High-density Flash memory devices
High levels of reliability
Performance comparable to today’s standard NOR Flash memory
AMD’s award winning service and support
Publication # 25260 Rev: C Amendment/0
Issue Date: September 18, 2002
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