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參數(shù)資料
| 型號： | 24LCS21A |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 1K 2.5V Dual Mode I 2 C Serial EEPROM |
| 中文描述： | 一千2.5V的雙模式的I 2 C串行EEPROM |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 115K |
| 代理商： | 24LCS21A |
1996 Microchip Technology Inc.
Preliminary
DS21161C-page 9
24LCS21A
4.0
WRITE OPERATION
4.1
Byte Write
Following the start signal from the master, the slave
address (four bits), three zero bits (000) and the R/W bit
which is a logic low are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24LCS21A. After receiv-
ing another acknowledge signal from the 24LCS21A
the master device will transmit the data word to be writ-
ten into the addressed memory location. The
24LCS21A acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24LCS21A will not
generate acknowledge signals (Figure 4-1).
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high to low during the self-timed
program operation will not halt programming of the
device.
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LCS21A in the same way
as in a byte write. But instead of generating a stop
condition the master transmits up to eight data bytes to
the 24LCS21A which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an
internal write cycle will begin (Figure 5-2).
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high to low during the self-timed
program operation will not halt programming of the
device.
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
VCLK WRITE ENABLE TIMING
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
WORD
ADDRESS
DATA
S
T
O
P
S
T
A
R
T
A
C
K
S
P
A
C
K
A
C
K
VCLK
SCL
SDA
IN
VCLK
T
HD
:
STA
T
SU
:
STO
T
VHST
T
SPVL
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| 24LCS21 | 1K 2.5V Dual Mode I 2 C Serial EEPROM |
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| 24LCS52 | Connectors |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LCS21A/P | 功能描述:電可擦除可編程只讀存儲器 2.5V Dual Mode RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LCS21A/S | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPRO - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LCS21A/SN | 功能描述:電可擦除可編程只讀存儲器 2.5V Dual Mode RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LCS21A/W | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPROM WAFER - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LCS21A/WF | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPRO - Gel-pak, waffle pack, wafer, diced wafer on film |
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