參數(shù)資料
型號(hào)： 24LCS21A
廠商： Microchip Technology Inc.
英文描述： 1K 2.5V Dual Mode I 2 C Serial EEPROM
中文描述： 一千2.5V的雙模式的I 2 C串行EEPROM
文件頁(yè)數(shù)： 7/16頁(yè)
文件大?。?/td> 115K
代理商： 24LCS21A
1996 Microchip Technology Inc.
Preliminary
DS21161C-page 7
24LCS21A
3.1
Bi-directional Mode Bus
Characteristics
The following
bus protocol
has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-4).
3.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
3.1.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.1.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Note:
Once switched into Bi-directional Mode, the
24LCS21A will remain in that mode until
power is removed. Removing power is the
only way to reset the 24LCS21A into the
Transmit-only mode.
Note:
The 24LCS21A does not generate any
acknowledge
bits
programming cycle is in progress.
if
an
internal
FIGURE 3-4:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(A)
(C)
DSCL
or
MSCL
DSCL
or
MSCL
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
24LCS21A/P 功能描述:電可擦除可編程只讀存儲(chǔ)器 2.5V Dual Mode RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
24LCS21A/S 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPRO - Gel-pak, waffle pack, wafer, diced wafer on film
24LCS21A/SN 功能描述:電可擦除可編程只讀存儲(chǔ)器 2.5V Dual Mode RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
24LCS21A/W 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPROM WAFER - Gel-pak, waffle pack, wafer, diced wafer on film
24LCS21A/WF 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPRO - Gel-pak, waffle pack, wafer, diced wafer on film
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