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參數(shù)資料
| 型號： | 24LC41P |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 1K/4K 2.5V Dual Mode, Dual Port I2C⑩ Serial EEPROM |
| 中文描述： | 1K/4K 2.5V的雙模式，雙端口串行EEPROM的I2C⑩ |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 150K |
| 代理商： | 24LC41P |
2004 Microchip Technology Inc.
DS21140F-page 3
24LC41
TABLE 1-2:
AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER
ACCESS PORTS)
DDC Monitor Port (Bidirectional Mode) and Microcontroller Access Port
Parameter
Symbol
Standard Mode
Vcc = 4.5 - 5.5V
Fast Mode
Units
Remarks
Min
—
Max
100
Min
—
Max
400
Clock frequency
(DSCL and MSCL)
Clock high time
(DSCL and MSCL)
Clock low time
(DSCL and MSCL)
DSCL, DSDA, MSCL and
MSDA rise time
DSCL, DSDA, MSCL and
MSDA fall time
Start condition hold time
F
CLK
kHz
T
HIGH
4000
—
600
—
ns
T
LOW
4700
—
1300
—
ns
T
R
—
1000
—
300
ns
(Note 1)
T
F
—
300
—
300
ns
(Note 1)
T
HD
:
STA
4000
—
600
—
ns
After this period the first
clock pulse is generated
Only relevant for repeated
Start condition
(Note 2)
Start condition setup time
T
SU
:
STA
4700
—
600
—
ns
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
0
—
—
—
0
—
—
—
900
—
ns
ns
ns
ns
ns
250
4000
—
4700
100
600
—
1300
3500
—
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1)
, C
B
≤
100 pF
Output fall time from V
IH
min to V
IL
max
Input filter spike
suppression (DSCL, DSDA,
MSCL and MSDA pins)
Write cycle time
DDC Monitor Port Transmit-Only Mode Parameters
Output valid from VCLK/
DWP
VCLK/DWP high time
VCLK/DWP low time
Mode transition time
Transmit-only power-up
time
Endurance
T
OF
—
250
20 + .1
C
B
—
250
ns
T
SP
—
50
50
ns
(Note 3)
T
WR
—
10
—
10
ms
Byte or Page mode
T
VAA
—
2000
—
1000
ns
T
VHIGH
T
VLOW
T
VHZ
T
VPU
4000
4700
—
0
—
—
500
—
600
1300
—
0
—
—
500
—
ns
ns
ns
ns
—
1M
—
1M
—
cycles
25°C, Vcc = 5.0V, Block
mode
(Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of Start or Stop
conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance model which can be obtained from our web site.
2:
3:
4:
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