參數(shù)資料
型號: 24LC21-P
廠商: Microchip Technology Inc.
英文描述: Connector; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes
中文描述: 一千2.5V的雙模式的I 2 C串行EEPROM
文件頁數(shù): 3/12頁
文件大?。?/td> 81K
代理商: 24LC21-P
1996 Microchip Technology Inc.
DS21095F-page 3
24LC21
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Symbol
Standard Mode
Vcc= 4.5 - 5.5V
Fast Mode
Units
Remarks
Min
4000
4700
4000
Max
100
1000
300
Min
600
1300
600
Max
400
300
300
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
F
T
T
CLK
kHz
ns
ns
ns
ns
ns
HIGH
LOW
T
R
T
F
:
STA
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
(Note 2)
T
HD
START condition setup
time
Data input hold time
Data input setup time
STOP condition setup time T
Output valid from clock
Bus free time
T
SU
:
STA
4700
600
ns
T
T
HD
:
:
:
DAT
0
0
900
ns
ns
ns
ns
ns
SU
DAT
250
4000
4700
100
600
1300
SU
T
T
STO
AA
3500
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
BUF
Output fall time from V
min to V
IL
max
Input filter spike suppres-
sion (SDA and SCL pins)
Write cycle time
Transmit-Only Mode Parameters
Output valid from VCLK
VCLK high time
VCLK low time
Mode transition time
Transmit-Only power up
time
Endurance
IH
T
OF
250
20 + .1
C
B
250
ns
100 pF
T
SP
50
50
ns
(Note 3)
T
WR
10
10
ms
Byte or Page mode
T
VAA
2000
500
600
1300
0
1000
500
ns
ns
ns
ns
ns
T
T
VHIGH
4000
4700
0
VLOW
T
VHZ
T
VPU
10M
10M
cycles 25
°
C, Vcc = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. C
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
B
= total capacitance of one bus line in pF.
I
specification for standard operation.
相關PDF資料
PDF描述
24LC21-SN 1K 2.5V Dual Mode I 2 C Serial EEPROM
24LC21A 1K 2.5V Dual Mode I 2 C Serial EEPROM
24LC21A-IP 1K 2.5V Dual Mode I 2 C Serial EEPROM
24LC21A-ISN 1K 2.5V Dual Mode I 2 C Serial EEPROM
24LC21A-P 1K 2.5V Dual Mode I 2 C Serial EEPROM
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