參數(shù)資料
型號(hào)： 24FC128
廠商： Microchip Technology Inc.
元件分類： EEPROM
英文描述： The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述： 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁(yè)數(shù)： 6/26頁(yè)
文件大?。?/td> 450K
代理商： 24FC128
24AA128/24LC128/24FC128
DS21191M-page 6
2004 Microchip Technology Inc.
4.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line, while the clock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
4.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
Data Valid (D)
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse, which is associated with this Acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX128) will leave the data line high to enable
the master to generate the Stop condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2:
ACKNOWLEDGE TIMING
Note:
The 24XX128 does not generate any
Acknowledge
bits
programming cycle is in progress.
if
an
internal
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(A)
(B)
(D)
(D)
(C)
(A)
SCL
9
8
7
6
5
4
3
2
1
1
2
3
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
Data from transmitter
相關(guān)PDF資料
PDF描述
24FC256 24AA256/LC256/FC256 Datasheet
24FC32 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC32-IP 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC32-ISM 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC32-P 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
24FC128-E/CS15K 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:128K I2Ca?￠ CMOS Serial EEPROM
24FC128-E/MC 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:128K I2C CMOS Serial EEPROM
24FC128E/MF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM
24FC128-E/MF 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:128K I2C CMOS Serial EEPROM
24FC128-E/MNY 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:128K I2Ca?￠ CMOS Serial EEPROM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*