參數(shù)資料
型號(hào): 24C16B
廠商: Microchip Technology Inc.
英文描述: 16K 5.0V E-Temperature serial EEPROMs(16K位,5.0V,1M次擦寫(xiě)周期,硬件寫(xiě)保護(hù),施密特觸發(fā)輸入的EEPROM)
中文描述: 16K的5.0V電子溫度(16K的位和5.0V,100萬(wàn)次擦寫(xiě)周期,硬件寫(xiě)保護(hù),施密特觸發(fā)輸入的EEPROM的串行EEPROM)
文件頁(yè)數(shù): 3/10頁(yè)
文件大?。?/td> 111K
代理商: 24C16B
1995 Microchip Technology Inc.
DS21081C-page 3
24C08B/16B
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
Min
Max
Units
Remarks
Clock frequency
F
CLK
100
kHz
Clock high time
T
HIGH
4000
ns
Clock low time
T
LOW
4700
ns
SDA and SCL rise time
T
R
1000
ns
Note 2
SDA and SCL fall time
T
F
300
ns
Note 2
START condition hold time
T
HD
:
STA
4000
ns
After this period the first clock
pulse is generated
START condition setup
time
T
SU
:
STA
4700
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
ns
Data input setup time
T
SU
:
DAT
250
ns
STOP condition setup time
T
SU
:
STO
4000
ns
Output valid from clock
T
AA
3500
ns
Note 1
Bus free time
T
BUF
4700
ns
Time the bus must be free before
a new transmission can start
Output fall time from V
min to V
IL
max
IH
T
OF
250
ns
Note 2, C
B
100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
T
SP
50
ns
Note 3
Write cycle time
T
WR
10
ms
Byte or Page mode
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2: Not 100% tested. C
B
= total capacitance of one bus line in pF.
Note 3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification.
SU:STA
t
HD:STA
t
F
t
LOW
t
HIGH
t
R
t
SU:STO
t
BUF
t
t
AA
t
SDA
OUT
SDA
N
SCL
HD:DAT
t
SU:DAT
t
AA
SP
t
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