參數(shù)資料
型號(hào): 24AA52_05
廠商: Microchip Technology Inc.
元件分類(lèi): EEPROM
英文描述: 2K 2.2V I2C⑩ Serial EEPROM with Software Write-Protect
中文描述: ⑩2K 2.2伏的I2C串行EEPROM與軟件寫(xiě)保護(hù)
文件頁(yè)數(shù): 3/28頁(yè)
文件大?。?/td> 350K
代理商: 24AA52_05
2005 Microchip Technology Inc.
DS21166J-page 3
24AA52/24LCS52
TABLE 1-2:
AC SPECIFICATIONS
AC CHARACTERISTICS
V
CC
= +1.8V to +5.5V
Industrial (I): T
A
= -40°C to +85°C
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
1
F
CLK
Clock frequency
600
4000
1300
4700
400
100
300
1000
300
kHz
2.2V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA52)
(Note 1)
2
T
HIGH
Clock high time
ns
3
T
LOW
Clock low time
ns
4
T
R
SDA and SCL rise time
(Note 1)
SDA and SCL fall time
ns
5
T
F
ns
6
T
HD
:
STA
Start condition hold time
600
4000
600
4700
0
ns
2.2V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA52)
(Note 2)
7
T
SU
:
STA
Start condition setup
time
Data input hold time
ns
8
T
HD
:
DAT
ns
9
T
SU
:
DAT
Data input setup time
100
250
600
4000
1300
4700
900
3500
ns
2.2V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA52)
10
T
SU
:
STO
Stop condition setup
time
Output valid from clock
(Note 2)
Bus free time: Time the
bus must be free before
a new transmission can
start
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike
suppression
(SDA and SCL pins)
Write cycle time
(byte or page)
Endurance
ns
11
T
AA
ns
12
T
BUF
ns
13
T
OF
20 + 0.1 C
B
250
250
ns
2.2V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA52)
14
T
SP
50
ns
(Note 1 and Note 3)
15
T
WC
5
ms
16
1M
cycles
25°C, V
CC
= 5.0V, Block
mode
(Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained from Microchip’s web site
at www.microchip.com.
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