參數(shù)資料
型號(hào)： 24404A
英文描述： AMD PowerNow!? Technology Platform Design Guide Application Note AMD PowerNow! Technology White Paper
中文描述： AMD的PowerNow??？技術(shù)平臺(tái)設(shè)計(jì)指南應(yīng)用筆記的AMD PowerNow！技術(shù)白皮書
文件頁(yè)數(shù)： 9/18頁(yè)
文件大小： 392K
代理商： 24404A
Implementing AMD PowerNow! Technology
5
24404A/0—November 2000
AMD PowerNow! Technology Dynamically Manages Power and Performance
Preliminary Information
Processor frequency is modified by writing to a 4-byte field in
the EPM I/O block that controls the bus frequency multiplier.
This is done internally to the processor and does not affect any
external signals or clocks. The external Bus Frequency (BF)
pins should be used for power-on self test (POST) and RESET
strapping only; the pin states are not modified when invoking
AMD PowerNow! technology.
For the AMD-K6-2E+ and AMD-K6-IIIE+ low-power processors,
operation can be maintained down to a core voltage of 1.4 V at a
processor clock frequency of 200 MHz. With a multitude of
intermediate steps between the rated maximum and minimum
of the processor, a system designer can pinpoint and implement
the optimal performance and power profile for any application
at any time.
Ease of Implementation
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Built-in bus frequency (BF) multiplier and VID control.
Dynamic VID pins for controlling V
CC2
regulator.
Programmable bus frequency (BF) with on-chip registers.
Default VID state for “safe” power-up.
Clock multiplier and regulator voltage is controlled by
software.
CPU uses BF pins.
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